CALICE MAPS Meeting, RAL, 12/07/06 ================================== Present: Jamie Crooks, Paul Dauncey, Mike Green, Yoshi Mikami, Renato Turchetta, Giulio Villani, Nigel Watson Minutes: Paul Minutes of last meeting: Not available at the time of the meeting; all the CALICE-UK website was down due to a hacker incident at Imperial. Management and schedule: Mike Green has taken on the role of Project Manager for CALICE-UK. He is updating the schedules and management organisation for all five Workpackages and so attended the MAPS meeting today. Mike has entered the top-level WP3 schedule and milestones into Project and has identified a few missing items, specifically the preparations for the two rounds of sensor testing. The first round of preparations will consist of layout and fabrication of the sensor PCBs, construction of the DAQ system, preparation of the various test stand hardware and integration and commissioning of the whole system at each site. This work will be scheduled to start on 1/12/06 and continue until the start of the detailed tests on 1/6/07. The second round of preparations should be much shorter as it will consist of layout and fabrication of a second PCB but otherwise only upgrades to the existing system. This will be scheduled for two months, 1/3/08 to 1/5/08. The upcoming dates on the top-level schedule were discussed. The next milestone is the Interim Design Review (IDR). This had been scheduled for around the end of Aug. However, this review is to allow the progression from the design schematics phase to the layout phase and so requires the full set of schematics to be completed. Jamie has estimated this should happen around late Sep so a date for the IDR of Wed 4 Oct was decided. This review could take effectively the whole day and will be a technical review of the schematics with external engineers. The other upcoming critical date is the submission of the first sensor for fabrication. The multi-processor ("shuttle") run dates for 2007 are not yet known but were 15 Jan and 20 Feb in 2006. We need to aim for the equivalent of the 15 Jan date, as a Feb date would delay us by a month. The Feb date should be considered as the fallback but a submission after this would seriously delay the project. Sensor design: Renato and Jamie had a meeting with Foundry B last month. This seemed quite positive and there was some exchange of data. Jamie has sent them an example pixel design although they have not yet responded with all the information Renato and Jamie requested, in particular the shuttle run dates for 2007 and the design tolerances ("corners") for diodes. They will meet again next week. The order is just below the EU single-tender limit but RAL admin would like to ask for more than one quote anyway. They will contact the foundries asking for formal quotes. As we are likely to be required to use the lowest bid, the specification needs to be carefully written and must include requirements on the dates for the shuttle runs. This whole exercise should be complete by mid-Aug so it will not hold up the design; the layout phase is when the real foundry-dependent work is done and this will start in Oct after the IDR, as stated above. Jamie also reported on work from the OPIC/MI3 project and progress on the CALICE design; see the usual web page (when it is next available!). The users of the OPIC sensor (including Phil Allport) reported missing codes in the sensor ADC output. Jamie traced this down to the Grey code being corrupted due to its distribution being through noisy parts of the sensor. Although not identical to the CALICE case, there are lessons for us and in particular, Jamie proposes to add parity bits to the timestamps at least to allow us to identify corrupted values. This can be done relatively easily as the memory cells are designed to be 16 bits, while only 14 are probably needed. For the CALICE design, Jamie has found voltage comparators seem to be disappointing and has been looking at using a reference circuit with a current comparator. This would have to be on all the time, as the settling time can be 10's of ms, and so it would have to be low power. This would allow the use of a continuous (unlatched) compatator and so would mean the clocking would not be distributed over the pixels, reducing the digital switching noise. Sensor simulation: Giulio has now done some of the 50x50mu2 simulations and he reported on the results of these (see slides on the usual web page). He has implemented a central N-well to represent the pixel circuitry and finds around 3/4 of the charge is absorbed here, reducing the signal seen in the sensing diodes to around 200e per MIP (to be compared with the 450e assumed by Jamie up until now). This is clearly a major change and we need to understand the main parameters which affect (and minimise) this. In particular, Giulio thinks the area of the N-wells is a major factor in the charge they absorb so this should be checked explicitly. If so, then it might be that increasing the sensing diode areas would increase the signal faster than the noise increase due to the extra capacitance, hence improving S/N. Giulio will investigate this. There was also a discussion on the amount of charge collected for particles going through the centre of the diodes as the central N-well seemed to collect a lot more than the sensing diode in this case. This needs further study. Physics simulation: Yoshi showed some slides on progress with Mokka; see the usual web page. The LCIO SimCalorimeterHit objects contain a variable which is supposed to represent the number of hits contributing to the energy in the pixel but this gave odd distributions so it may not be filled correctly. This needs further study which may have to be done at the GEANT4 debug level. Anne-Marie had provided some slides on the status of the post-Mokka digitisation simulation; see the usual web page. The program is ready but needs realistic charge diffusion values from Giulio's simulation, which he will provide to Anne-Marie soon. The discussion revealed a discrepancy between the subpixel size used in Mokka (5x5mu2) and the one used by Giulio to subdivide the charge deposit position (a 6x6 array within the pixel, i.e. for 50x50mu2 pixels, this is 8.3x8.3mu2). The same step size should be used for consistency so it was decided to use 5x5mu throughout. This means Giulio will need to subdivide the pixels in his simualation into a 10x10 array, which will slow down the simulation. He will therefore produce the charge deposit positions for 21, rather than 10, steps in a triangular array. Next meeting: This will be on Wed 6 Sep at 1pm in R76 as usual. The IDR date is fixed for Web 4 Oct at RAL, start time not yet decided.