CALICE MAPS Meeting, RAL, 05/10/06 ================================== Present: Jamie Crooks, Paul Dauncey, Anne-Marie Magnan, Yoshi Mikami, Owen Miller, Konstantin Stefanov, Renato Turchetta, Mike Tyndel, Nigel Watson, John Wilson Minutes: Paul We welcomed Owen Miller, the new CASE student at Birmingham/RAL, to his first meeting. Minutes of previous meeting: No corrections. It would be good to make the ILC community more aware of our work and Paul asked who would be able to give an overview talk at the Valencia ECFA meeting in November, probably including a run-through of the presentation at the CALICE-UK meeting in Manchster on Nov 3. There were no immediate volunteers. The talk would be mainly to physicists rather than engineers but could be close to Giulio's Siena talk; Giulio himself might be a candidate for this. Giulio should send Paul the final version of his Siena talk to put on the web site. Renato looked into the CERN framework agreement but concluded it would be too expensive; the cost is 0.5MCHF divided by the number of users. Sensor design: Renato has now gone through the tenders and there are no big suprises. Foundry A is only able to do 0.35mu at present and so quoted for this. They are gearing up for 0.18mu but this will not be ready until later in 2007. Foundry D quoted a cost above our budget and even then we would be restricted to two engineering runs. They have also asked for $200k if we wanted to do development of deep-p implant. Foundry B have given a quote which is close to budget, depending on the options we choose. Four metal layers plus stitching would be affordable but six layers would be ~10-20kpounds over. However, given the dead regions for the logic and memory, then there is less motivation for stitching and six layers without stitching would be within budget. It was not clear if Foundry B would do deep-p well for a shuttle run. The quote is for 12 wafers in 6 process splits (i.e. two wafers in each split) so it would be useful to make two wafers with deep-p wells as a test. However, it is not clear how deep-p would be achieved given the other designs on the same wafer. Renato will follow up on this, including meeting a Foundry B visitor at RAL soon. Jamie reported that they have identified two architectures for the main part of the pixel circuit: 1) The correlated double sampling (CDS) circuit with reset which Renato has been studying. 2) The more "classical" preamp and shaper circuit Jamie has been looking into. The comparator design would be common to both cases and this should be achievable in pure n-mos, hence absorbing no charge from the epitaxial layer. This would also be relatively low power compared to a design including p-mos; Jamie thinks the comparator will contribute around 1uW/pixel. For 1), Renato thinks there would need to be only one p-mos transistor which would be around 2x2mu2 in area. Although Kleinfelder has shown purely n-mos circuits using two source followers to reduce the kT noise, Renato thinks we need a charge amplifier with open-loop gain, which is hard to do without p-mos. A pure n-mos amplifier would have to be multistage, making the reset more complex and having increased power. Renato has not looked systematically at all process corners yet but for a specific point, a MIP signal (assumed to be 250 electrons) corresponds to around 40mV. He finds a small fixed pattern noise of around 0.5mV ~ 3ENC but the temporal noise dominates at around 20ENC. This noise goes as sqrt(input capacitance) and the only way to reduce it substantially would be to reduce the capacitance through changing the diode size or spacing. This circuit requires a reset after each hit. For 2), Jamie has found a big variation in process corners of around a factor of two in response. However, while this gives the range expected over many wafers, the variation in processing within a single wafer would normally be much smalled. A MIP signal (again assumed to be 250 electrons) gives a response between 50-90mV and the noise is around 6mV, which it therefore something like 20-30ENC. It would not be possible to make this circuit from p-mos only and it would probably need more p-mos transistors than design 1). The total power of the preamp and shaper would be around 6uW/pixel when powered. This noise in this design would be expected to be less sensitive to the input capacitance. Both designs could run from 1.8V (reduced from 3.3V) which will keep the power lower and give a (small) reduction in the n-well charge collection. It is clear that the number and layout of the diodes will be constrained by their effect on the input capacitance and hence the noise. Hence, it is important that the noise vs. input capacitance for these designs is estimated quantitatively within a short period; this was thought to be feasible within the next two weeks and should be circulated asap, before the next meeting. Sensor simulation: Konstantin reported on his 2D simulation studies; see the usual web page. He simulates the diffusion in the vertical direction and also in one of the two dimensions within the sensor plane. The charge is constrained within 1mu in the third dimension and cannot leak out in this direction (although it can at the ends of the simulated pixel). Konstantin simulates the central n-well and charge collection diodes and so his simulated region corresponds to a diagonal strip through the pixel. This means the standard pixel distance from the central n-well correponds to sqrt(2)*50mu ~ 70mu in this dimension. The effect of the diodes and n-well only extends down a few mu into the epitaxial layer and so significant amounts of the charge freely diffuse past these structures without being absorbed. Hence, although a thicker epitaxial layer produces more charge, it is not clear that it gives a proportional benefit in terms of collected signal. Konstantin also showed some slides from Giulio; see usual web page. Giulio seems quite large increases in the collected charge when increasing the diode size. Konstantin sees a qualitatively similar effect but quantitatively, Konstantin's and Giulio's simulations do not agree; e.g. compare Konstantin's slide 3 with Giulio's slide 4, the lower left and right plot red curves, for the effect as a function of diode size. (N.B. Konstantin's 2D simulation means the diode sizes he uses are 1x1mu2, 2x1mu2, 4x1mu2 and 8x1mu2, compared to Giulio's 0.9x0.9mu2 and 1.8x1.8mu2.) Giulio's slides show the smallest signal within a pixel is seen for MIP deposits close the pixel boundary, when only ~200 electrons are collected. This region even collects less charge than when the MIP is deposited right underneath the central n-well. This lowest point determines the requirements on the noise to meet the S/N needed. In particular, Konstantin showed that the charge collected for a MIP underneath the central diode is increased by bringing the diodes closer to the centre. However, this change is very likely to reduce the charge collected from a MIP near the pixel boundary, which is the more difficult case and so this implies more uniform accpetance would be achieved by moving the diodes further away from the centre. Konstantin also suggested using the diode itself to connect to the central pixel circuitry rather than a metal contact. However, Jamie stated the minimum diode width is 0.9mu, meaning the connection would be similar in size to the diode itseld, which might imply a significant increase in capacitance. There are several effects which are not included in these studies. The main one is the Landau MIP spread which is very wide for small epitaxial thicknesses. Chris Damerell has made plots of this; see Paul's slide XXX from his original talk to the PPRP, at http://www.hep.ph.ic.ac.uk/calice/official/050201pprp/050201.ppt (or .pdf). Also, any pixel to pixel variation will mean the common threshold cannot be set optimally for every pixel. Hence, the effective signal/noise will always be reduced from the value estimated in these studies. It was thought that a simulated value of S/N ~ 15 would be sufficient to ensure that the required effective S/N ~ 10 would be achievable in practice. Note, S/N ~ 15 has not been achieved yet and this should be the target of the diode geometry optimisation. This is turn requires knowledge of the noise for a given geometry. This has two parts; the noise vs. input capacitance, mentioned above, and the input capacitance for a given diode geometry. The latter is not straightforward; the capacitance is thought probably to be dominated by the capacitance to the neighbouring region and so would be proportional to the diode circumference. However there may also be a smaller term proportional to area. Jamie can produce quantitative estimates of these capacitances. Physics simulation: Yoshi showed some slides on the size of the physical energy deposits seen in the simulation; see the usual web page. The MIP peak does appear at 3.7keV as expected but there is a large spread, reflecting the wide Landau as mentioned above. There is a low energy tail which seems to be due to edge effects as particles cross the pixel boundaries, although this will be substantially smeared out by the diffusion, which is not included here. A large low tail also appears in the standard simulation although this seems much bigger than for the MAPS case. It is probably related to the sub-MIP deposits expected from photons in the showers which interact throughout the silicon thickness; for the MAPS case, they are only seen if the interaction occurs in the 3% of silicon which is the epitaxial layer. Schedule and IDR: The IDR, scheduled for the previous day, had been postponed due to the issues discussed above with the status of the design. The schedule is constrained by the deadlines for the shuttle run submissions. For Foundry B, the one we are currently aiming for is 22 Jan with the next after this being 17 Apr. Paul asked if there are any aspects of the design or optimisation which we would do differently if we knew now that we were submitting to the Apr rather than Jan run. The answer appeared to be no, so there is no need to make a decision on this yet; we will continue to try to make the Jan date, with the Apr date as the fallback. Note, a delay of three months would put a lot of pressure on the testing periods later and would require us to prepare for the tests as far as possible in advance. There was general agreement that the main aim of the first sensor production was to demonstrate that the pixel itself could perform and so it is important to get the S/N to a sufficient level. Producing a sensor on schedule which does not meet the S/N requirements would not be so useful. To make the Jan deadline for submission, then it is clear the IDR cannot be delayed by more than a few weeks. However, Jamie could start doing some of the layout of the stable parts of the sensor before the IDR if he completes the design some time before the review. However, the pixel circuit and diodes obviously cannot be laid out until the above issues are settled. Mike was keen for a decision to be made between the two pixel circuits and not to implement both in the first sensor. The choice will require a balance of reliability of the design against power and S/N. This information might only be available quite close to the submission deadline. Next meeting: The next standard meeting will be on Fri 20 Oct at 13.00 in R76 as usual. The postponed IDR was rescheduled to be on Tue 31 Oct also starting at 13.00 and will also take place in R76. Renato will contact the same external reviewers as agreed previously.