CALICE MAPS Meeting, RAL, 13/11/06
==================================
Present: Jamie Crooks, Paul Dauncey, Yoshi Mikami, Owen Miller, Marcel
 Stanitzki, Konstantin Stefanov, Renato Turchetta, Mike Tyndel, Giulio
 Villani, Nigel Watson

Minutes: Paul


Minutes of last meeting: No corrections.
 Marcel was introduced as this was his first meeting.


Conferences: Konstantin reported that the talks at Valencia seemed to go
 well and MAPS got a good mention in the summary talk by Erika Garutti.
 
 Konstantin also reported that a talk by L. Ratti (Pavia) on MAPS for
 the ILC vertex detector had contained a pixel circuit design similar to
 ours; see link on the usual web page. It uses a biased deep n-well to
 collect the charge which is very large, 30x30mu^2, and is equivalent to
 a 100fF input capacitor. They have 1us shaping and the design is
 implemented in 0.13mu technology. This gives a noise of ~40 ENC; Jamie
 will scale his values to crosscheck how this compares with his
 calculations.

 Yoshi reported that there had been a MAPS talk in the DAQ session by
 L.Piemontese; see web page. This concerns the DAQ readout of a vertex
 detector MAPS system for EUDET.

 Following his talk, Konstantin had a long discussion with Marc Winter
 (Strasbourg) who has been working on vertext detector MAPS for some
 time. He proposed some level of collaboration and discussion of
 results. He stated they get approximately 20% agreement with the same
 sensor simulation as used by Giulio when comparing with their beam test
 results. It was thought they had not done a detailed laser scan as we
 plan to do. Marc's group work with STS (Thompson) Microelectronics in
 Grenoble and have developed a 0.13mu process which cuts a trench around
 each pixel through the epitaxial layer. This uses similar technology to
 the holes made in 3D detectors and gives a 1mu wide, 20mu deep groove.
 With our pixel size, this would be a 4% dead area. This is a very
 non-standard process, which would undermine one of the main motivations
 for MAPS, but is clearly an interesting development.

 There will be a meeting on silicon sensors for ECALs at the EWHA
 University, Seoul, on 12-14 Dec; see link on the usual web page. Yoshi
 can attend this. The talk should aim at a technical rather than
 simulation description, similar to Konstantin's Valencia talk with any
 updates over the two months.


Sensor design: Renato reported that Foundry B have said the deep p-well
 process qualification can be done in time for the Jan shuttle run 
 (although this is now redundant for us). They have quoted a cost of
 $90k +/- 10% exclusive of VAT. It is not clear if we will need to pay
 VAT yet; Renato will chase this up with the RAL administration. The
 worst case figure is then $120k ~ £65k pounds. RAL will pay £35k of
 this so CALICE will need to find the rest, presumably from the
 working allowance. Paul will alert the OsC of this issue before the
 28 Nov meeting.

 The firm cost and exclusivity of rights to the process still need to
 be settled but Renato hopes this can be completed by the end of Nov.
 Konstantin and Giulio (and Marcel to some extent) will need to know
 details of the process also. They are covered by the non-disclosure
 agreement (NDA) RAL signed with the foundry and so can attend the
 meetings. Hence, Renato will include them in any future meetings.

 Following comments reported from Valencia, Paul raised the issue of the
 epitaxial layer thickness. The 12mu currently being assumed is because
 the only other thicknesses being offered were less. A thicker epitaxial
 layer would give more charge and would probably improve the S/N on the
 hit picel but might also increase cross talk; the charge liberated in
 the deepest parts of the epitaxial layer would be more likely to
 diffuse further before being absorbed by a diode at the top. The
 optimal thickness is still to be determined.

 Konstantin raised the issue of having some traces added for analogue
 readout of the pixels, to allow the signal size and timing to be seen
 directly. This had been discussed in the PDR and will be implemented
 although whether standard pixels in the main sensor or test structure
 will be used has not been decided.

 Jamie showed some slides of updates to the pixel circuit designs; see
 usual web page. In extending the shaping time, he has simplified the
 circuit a little but this means it would not be possible to go back to
 the faster shaping without changing the design again. The shaper will
 now go over threshold for ~600ns. This means several contiguous 150ns
 comparator samples will fire for each particle and it might be possible
 to record only the first and last. It is not clear how this works with
 the logic scheme of ORing the channels in groups of six. There is also
 potentially amplitude information in the time-over-threshold value
 although it is not clear how useful this would be.

 The preshaper circuit will saturate after integrating between 10k
 and 20k electrons within a bunch train. This corresponds to 10-20 MIPs,
 assuming deep p-well, although Jamie would reduce the gain a little
 if deep p-well is certain so as to give a little more overhead. The
 presampler circuit can absorb at least 30k electrons; note this
 saturation is not cleared with the reset following a hit.

 Both circuits give very comparable noise ~25 ENC, where the preshaper
 nosie calculation assumes 20fF input capacitance, i.e. 1.8x1.8mu^2
 diodes. Hence, it is not clear which circuit is better; the preshaper
 saturates sooner but the presampler needs a reset after each hit and
 therfore has more deadtime. Other issues are which is more viable,
 i.e. likely to work, and which is more likely to function better when
 power pulsing, which will be an essential feature of the final system.

 It would be possible to implement both, but there are only a total of
 four pixel variants foreseen in the first round so the issue is then
 whether there are other features which have a higher priority for
 varying. It was agreed that two diode layout variants would be
 sufficient, since if the sensor simulation can be tuned to agree with
 these, then inter/extrapolating between them with the simulation would
 allow us to optimise the layout for the second round. The two diode
 variants should span the parameter space to some extend, e.g. a 2x2
 array of 1.8x1.8mu^2 diodes and a 3x3 array (except for the central
 diode) of 0.9x0.9mu^2 diodes might be sufficient. It would also be
 good to make sensors with and without the deep p-well. However, this
 is possible through the wafer processing groups (we can have up to
 six different process group of two wafers each) and so would not take
 up any of the four pixel variations within the sensor. No other major
 variants were suggested so it was decided that the two circuits should
 both be implemented as two variants, with the diode layout as the other
 two, giving four combinations total.

 The IDR, which was postponed from 4 Oct, was fixed to be on Mon 18 Dec.
 We will use the same reviewers as previously assumed if they are
 available; Renato will contact them. Konstantin can no longer qualify
 as an external reviewer so we may need a new third reviewer, from
 outside RAL/EID.

 Mike raised the issue of the location of the comparator. If we are
 sure we will have deep p-well, then it makes sense to place the
 comparator in the pixel and reduce the size of the dead logic region.
 Obviously, we cannot yet be sure of this but we should assume the deep
 p-well will be used for now. The next element up in the circuit is the
 pixel mask; this could also be moved to within the pixel although
 setting the mask bits would require a more complex shift register path.
 This would not only save on the dead area but Marcel suggested it would
 also allow the mask bit to turn off the power to the pixel. Unless a
 large fraction of the pixels are dead (and hence masked), the power
 saving would be small but this could prevent a bad pixel disabling the
 neighbouring pixels.


Sensor simulation: Giulio had just got back from IEEE and had not yet
 analysed the simulation runs which had completed.

 One issue for future simulations will be modelling the deep p-well;
 hence the need for Giulio to attend the next meeting with the foundry.
 However, to a first approximation, then simply leaving the whole
 n-well area out of the simulation should be sufficient.


Sensor testing: This is a new agenda item as we will need to produce
 a readout system for the sensors before the first round are returned
 in Aug next year. The system will be mainly produced by Imperial but
 some effort from RAL/PPD on the firmware could be used. The Imperial
 engineer, Matt Noy, will start work on this within a few weeks. The
 same system will be used to test ASIC chips designed in France for
 the standard ECAL readout, so the system will be somewhat more general
 than just MAPS readout. We will also need five or six copies of the
 readout system so the cost cannot be high.

 There have been some discussions at Imperial on the general concept,
 which will be a commercial FPGA development board, a generic interface
 board to this and specific PCBs to hold the MAPS sensors or ASICs. The
 I-DAQ board was previously suggested as an alternative to the FPGA
 development board, but these are now not available in the numbers
 needed so this idea has been dropped.

 Giulio has recently bought a Xilinx development board of the same type
 as used by Renato's group for MI3 sensor testing; see web page for the
 flyer for this board. This has ~100 user I/O pins, which might not be
 sufficient for the MAPS cosmics test stack, where four sensors need to
 be run synchronously. It is also too expensive for our use.


Physics simulation: It is clear that several of the issues which would
 decide between the two circuits need input from the physics simulation.
 Specifically, the importance of the saturation after 10 MIPs and the
 deadtime induced by the reset are things which can be estimated by
 this route.

 Nigel reported that there had been a simulation meeting earlier in the
 day where the tasks to produce these results had been discussed and
 assigned. The technical code is not yet all in place; the GEANT4
 (Mokka) program, which produces the exact energy deposits (hits) is
 running with 5x5mu^2 subpixels matched to Giulio's simulation steps.
 However, the next step is to convert this into a list of hit pixels
 of size 50x50mu^2. This requires charge diffusion (from Giulio's
 simulation), addition of noise, implementation of the threshold and
 removal of pixels in dead areas. This "digitisation" step is partially
 implemented but not yet complete.

 The GEANT4-level code can be used for the first study needed, which is
 of the occupancy from the beam-related backgrounds. Nigel has estimates
 of the event rates and these need to be simulated to give an idea of
 the rate of hits in the ECAL.

 Post-digitisation, the plan is to initially combine the MAPS pixels
 into 1x1cm^2 pads equivalent to the standard ECAL pads. The number of
 pixels can then be scaled to give an equivalent measure to the standard
 analogue ECAL so they can be compared directly. This of course ignores
 much of the power of the MAPS granularity but will give a basic check
 that the MAPS does not degrade the measurement (we hope). As a quick
 step, a simple module to fake up the proper digitisation may be used
 so the subsequent code can be used.


Schedule: Paul showed the latest Gantt chart, updated to reflect the
 later shuttle run date of 17 Apr; see usual web page. The three month
 delay in the first sensor fabrication has been absorbed by shortening
 the first test period by one month and the second sensor beam test
 period by two months. To compensate to some extent for this latter
 change, we will aim to put the first sensors in a beam test, rather
 than only sensors from the second round. CALICE will be running in the
 FNAL beam line later next year, which is the sensor test period but we
 also have access to the DESY electron beam line through the CALICE-DESY
 group contacts. By taking the four-layer cosmic sensor stack originally
 planned (in the PDR) and using this, then it should be straightforward
 to see tracks in a beam and it would give a much higher rate than the
 0.01Hz assumed for cosmics. By adding various thicknesses of lead in
 front of the stack, it would be possible to sample EM showers at
 various radiation length depths, allowing a significant comparison of
 data with simulation.

 Konstantin commented that the second design period seems short,
 although it has not been squeezed relative to the original schedule.
 The six months allocated is not relaxed but is for (re)design of items
 which are only discovered during the tests. Things which are known to
 be missing, such as the on-sensor threshold DAC, can be designed
 starting as soon as the first sensor design is submitted. 

AoB: Marcel raised the issue about FNAL collaboration. FNAL have an ILC
 group which has been considering joining CALICE for some time. They
 also have very good facilities and significant effort. They have
 contacts in SiD (but not in the calorimetry side). Marcel has
 discussed the MAPS project with them and they seem interested in some
 level of collaboration. FNAL could clearly become a powerful institute
 in the ILC and so it would politicially be useful to have their
 support. However, the practical issues of using their facilities mean
 it would be difficult to do much more than exchange ideas for now.
 Marcel will remain in touch with them to see how things develop.


Next meeting: TBD; either Wed 29 Nov or Thu 30 Nov. Also, the IDR will
 be on Mon 18 Dec.