CALICE MAPS Meeting, RAL, 19/01/07 ================================== Present: Jamie Crooks, Paul Dauncey, Anne-Marie Magnan, Yoshi Mikami, Marcel Stanitzki, Konstantin Stefanov, Renato Turchetta (for part), Giulio Villani Phone: Owen Miller, Nigel Watson Minutes: Paul Minutes of previous meeting: No corrections. Background simulation: Owen presented work on the machine backgrounds, see usual web page. Even with some cuts on the generated particles, it taken 150 hours per bunch crossing to simulate. Hence, the statistical errors on the results are large; e.g. the 2 particles directly hitting the ECAL (here being barrel and endcap) have an error of +/-2. The minijets (two-photon production of hadrons) are generated by GuineaPig rather than Pythia but these are thought to be similar. Paul pointed out that Valeria Bartsch at UCL is looking at machine backgrounds in the context of SEUs for the DAQ; it might be profitable to communicate with her on this. Sensor design: The representative from the foundry visited RAL again last week. He did not provide the deep p-well process details; these were supposed to have been available from Jan 7, but have not yet been released. This is thought to be due to the contract not having quite been finalised and is not due to any technical problems with the new process. The number of process splits required by the foundry for the deep p-well is also not yet known; we cannot change the masks used in the splits so presumably we will vary the epitaxial layer thickness in the remaining splits available. The foundry is keen to review the pixel design for us. They have said the design can even violate their design rules and they will then advise on whether it is likely to work or not. This review can be done relatively early and so should not delay the submission, which is now tight (see below). The non-disclosure agreement should work both ways, meaning that they would not be able to reuse parts of our design having seen it. Jamie will send them the pixel designs around the first week of Feb, when the layout is likely to be effectively complete. This corresponds to when the foundry representative is next likely to visit. The submission date has been brought forward by about a month and is now Mar 12 (previously Apr 17). Jamie thinks this is tight but achievable. This also means that the sensors will be returned a month earlier than previously thought, which would put us only two months behind the original schedule. The foundry quotes a fabrication time (in working days) of 20+1.5*(number of mask layers). Guesstimating the number of layers as 30 gives 65 working days, which is 13 weeks. This would imply the sensors would be completed by Jun 11. Given that the submission date is only seven weeks from now, it was thought best to fix the date of the pre-submission Final Design Review (FDR). This was set for Wed 28 Feb and will be a day-long review, so starting at 10.00. We will need two external reviewers and Renato will find these; Mark Prydderch and one of either Nicola Guerrini or Andy Clark would be ideal. This review will cover any changes to the schematics since the IDR and then the layout itself. Jamie then reported on the sensor design progress; see slides on the usual web page. Although the logic column layout is larger than he estimated, it should still fit into four pixel widths, i.e. 200mu. Their current plan is to have a 4mu wide deep p-well "guard ring" around the outer edge of each pixel which contains the digital circuitry including the 5-bit configuration SRAM, and a ~4mu diameter deep p-well octagon in the centre containing the analogue circuitry, therefore keeping them well separated. One complication is that the SRAM is actually 8mu wide and so would physically sit half in the pixel and half in the neighbouring pixel's deep p-well. This would cause complications with the pixels near the edge of the sensor or next to the logic columns. The layout will start with the sample circuit as it is more complex and this will be minimally changed for the shaper case. In particular, the common comparator layout will be identical. The capacitors cannot now be made as intended using metal layers as the foundry design rules require only the top two metal layers to be used and this adds significant extra capacitance to the small values needed. Jamie has moved to using n-well capacitors and has re-simulated the circuit for these; see the simulation results document on the usual web page. He sees no significant changes compared to the previous simulation. He will have to use smaller than standard capacitors but the capacitor ratios are the most important quantities and these should be reasonably well-defined. N-well capacitors are non-linear but this may actually help in reducing large signals. The "guard ring" of deep p-well around the pixel will help to reflect charge back into the pixel as there is a potential difference across the boundary. However, the minimum efficiency occurs when the particle crosses the pixel close to the edge or corner. The deep p-well reduces the effective epitaxial layer by its thickness (~2mu) and so the guard ring would reduce signal charge close to the boundary even further. The obvious alternative would be to place all the deep p-well in the area of highest efficiency, i.e. at the centre of the pixel. However, this would make separating the digital and analogue more difficult and may also deflect charge away from the centre (and hence the diodes) and towards the neighbouring pixels. It was not clear which layout would be better overall (see below). Sensor simulation: Giulio showed some results of simulation runs of the deep p-well; see usual web page. This was not the same as the nominal layout Jamie described previously but a guess based on a previous discussion, with a 16x16mu2 central n-well surrounded by a deep p-well of 17x17mu2. The central n-well still is able to collect charge as the deep p-well boundary is thin, but the amount collected is ~1/5 of that collected by the diodes, except where the charge is deposited directly into the n-well. Konstantin suggested allowing a larger deep p-well around the n-well components to reduce this further. The minimum value is still seen for particles in the corner, where ~280e- is collected (but without the deep p-well which would reduce this to something like ~240e-). The simulation is of a depth of 32mu, of which the epitaxial layer is 12mu, although some charge from the bulk below the epitaxial layer can leak in, making an effective eptaxial layer (in terms of charge) a few mu thicker. The simulation is a numerical solution of the diffusion equations and so has no statistical errors. However, the mesh size used can be non-symmetric and so, particularly for coarse meshes, can give apparently asymmetric results (as observed by Anne-Marie, see below). Jamie thought a more realistic layout would be possible within ~two weeks. However, the major decision needed is whether to put most of the deep p-well around the edge (as a guard ring) or in the centre (to even out the efficiency). Giulio will do a simulation over the next week of both of these options with a rough estimate of the deep p-well sizes for each. Following this, the accurate layout can be simulated with 3.6x3.6mu2 and 7.2x7.2mu2 to check the S/N of each. Anne-Marie will also need a full 21-point fine-mesh simulation of a semi-final layout for the physics simulations studies. Physics simulation: Marcel showed slides of his initial physics studies; see usual web page. He confirms previous studies that the noise will dominate over physics for DAQ rates (although the machine background is still a large unknown). He finds a useful rule of thumb that there are roughly 100 pixels hit for each 1GeV of EM shower energy. He looked at dead area effects (before digitisation is applied) and hopes to get results on the effect of the dead area on EM shower resolution soon. A first try at non-electron track stub-finding in the ECAL (mainly for SiD applications, i.e. when there is no TPC) looks promising. Yoshi showed some updates of his studies; see usual web page. He finds changing the minimum step size from 5mu to 0.5mu does not qualitatively change the "missing energy" effect for small cell sizes, but it does change the plateau value so this is not understood. He will check if the shoulder at low cell energies (~1/3 of a MIP) changes for the smaller minimum step size. The conclusion on his studies of contiguous cells (either for 36 or 48) is that there is little correlation within groups of these sizes, even for large EM showers, so the numbers of pixels hit are not very different from random. Anne-Marie gave some information on the digitisation modules; see usual web page.She will put the digi Marlin processors in the CALICE cvs repository but this would not be appropriate for analysis code. The digi step is relatively quick (<30s/event for 200GeV electrons) compared to the Mokka step (~3mins/event for 200GeV electrons). The logic column dead areas have not yet been implemented. She finds a resolution of 17%/sqrt(E) when using the GEANT4 ideal hits, which is different to Yoshi's finding of 13%/sqrt(E). Yoshi uses a file which has 50x50mu2 pixels generated directly, not via the 5x5mu2 subpixels needed for the digitisation. Yoshi will send his files to Anne-Marie so she can check her code with his files to see where the differences arise. Due to the leakage of charge from the bulk, the effective charge generation depth is larger than the nominal epitaxial layer. Anne-Marie finds a charge liberated in Giulio's simulation of over 1300e-, which corresponds to around 17mu of depth. Since GEANT4 does not allow for leakage, then the epitaxial layer in the simulation needs to be increased to something like 17mu. It would be useful to get a accurate effective depth directly from the simulation; Giulio will calculate this. The simulation currently models all pixels in an equivalent way, including those in the logic columns which will later be treated as dead. This would only be correct if the logic column areas absorb charge in a similar way to normal pixels. This would require similar areas of n-wells to the diodes and deep p-well to that in normal pixels, which would be difficult to arrange. The two extremes would be to put deep p-well below all the logic columns (to prevent as much absorption as possible) or to leave it out (and hence asborb as much as charge as possible). Konstantin thought it would be dangerous to have free charge not being absorbed so leaving out deep p-well is probably better. [Note from Konstantin following the meeting: "Our ISIS1 chips has an array of 16x16 cells, at the bottom of which there are 16 column source followers. The array is in the centre of a large chip, with nothing around it. As charge is generated outside the active area (that area is quite big), it diffuses and ends up in the top row and the 2 side columns. There is nothing to protect them from this parasitic charge collection unlike the bottom row, which is shielded by the 16 source followers. As you can see in the picture the top row and the 2 side columns are always full of charge, and the bottom row is clean. The five frames have been taken after 200 ms exposure to X-rays. I hope this is convincing. What we should have done is to place a guard drain around the active pixel area." The picture he refers to above is in a ppt file on the usual web site.] Calorimeter review at LCWS07: Paul has got a copy of the guidelines for the tracking review at the ACFA meeting in early Feb; see usual web page. These imply the presentations will be detector-concept based and this has been assumed during discussions within the CALICE SB. [Note added following the meeting: Chris Damerall clarified that this was not the intention and that CALICE should expect to put in one document and have a presentation at LCWS07, not be as part of LDC. This means the MAPS input will be a part of the overall CALICE presentation.] Marcel has produced a draft of a submission and will send this to Paul. However, as Paul pointed out, the submission will be organised and written by CALICE as a whole, of which the MAPS is one part. Hence, writing assignments will be distributed by the CALICE SB at a later date (probably following the AFCA tracking review in Feb) so it is premature to start on anything yet. We could separately write an LC Note on MAPS but this would have more impact if it included real sensor results. In addition, a major part of such a note will need to be the physics simulation results to argue for the MAPS option and there is still much work to be done in this area. Korean workshop: Yoshi had given a presentation on MAPS at the silicon detectors workshop in Korea in Dec. He reported there were three main comments: 1) How to optimise the epitaxial layer thickness; this will be a balance of the signal size against charge diffusion 2) The effects of the dead areas and how they can be reduced. The 42 contiguous pixels are not at the limit and could be increased in future, possibly by using more than one metal layer to track the pixel signals to the logic columns. 3) What is the purpose of the non-sensitive bulk silicon. This is straightforward; thinning would make the sensor fabrication more complicated and more expensive. Next meeting: The next standard meeting will be on Thu 8 Feb at 13.00 in R76 as usual. There is also part 2 of the IDR next Thu 25 Jan at 13.00 and, as mentioned above, the pre-submission FDR is now scheduled for 10.00 on Wed 28 Feb.