Things that should be looked for the benfit of the second sensor design:



Comparison of performaces between preShape (1) and (2) and preSample (3) and (4) - to date, data has been displayed by "region" which is a column containing two variants of pixel - regrouping the data to correspond to differnet pixel architectures would be more appropriate and help selection of a single pixel design for implementation in ASIC2.

Full speed operation: Run the sensor at bunch-train rep rate 189ns (min?) and check performance - noise hits etc.  Will require some adjustment of non-overlapping clocks & FPGA sequencing, etc.

Noise rate:  Is it possible to run the sensor at the target 10e-6 noise rate?


Edge effects - do pixels adjacent to the logic report higher noise rates?  Is this acceptable?


Temperature effects - noise hits vs temperature?

Low power operation - is it possible to run the sensor at lower power without detrimental effect on noise rate?

Gain uniformity - source?

Linearity - use the laser to inject range of signal sizes, compare with simulations

Crosstalk analysis - use laser to characterise the crosstalk in the bulk pixels - does it compare with simulation --> are the diode positions ok for ASIC2?




Key decisions:

Selection of a single pixel architecture
Selection of a pixel pitch (50/75/100um)