We have hit a problem with the MAPS which might require us to
spend non-trivial amounts of extra money, probably in this FY.
I thought it would be worth warning you of this briefly before
the meeting on Thursday.

It turns out we will lose a lot of the ionisation signal charge 
into the readout circuit unless we make an extra implant layer 
under the circuit to cut off the signal from the circuit. This 
is currently non-standard for MAPS fabrication processes. The
company who will do the fabrication say it would be possible
(they have a similar process but with the opposite polarity) but
they would need to spend a month qualifying the process for use.
They would need us to pay for this; they quote $80k ~ 50kpounds
to do the development. This seems essential if we are to get a
good enough S/N so I think we have to find the money. Also, we
will need to do this in this FY to keep to a sensible schedule.

RAL/EID will benefit from this more generally than CALICE as their
other MAPS work would also be improved by using such a process.
Hence, I have asked that they split the cost with us. I have had
no response yet but I hope it is likely they will contribute. Hence
we would have to find ~25kpounds which we didn't expect. Clearly, this
is the sort of thing that the working allowance is for so we will need
to inform the OsC at the meeting in a few weeks.

One other aspect of this; qualifying this process will take extra
time and we will no longer make the Jan fabrication submission deadline. 
The next date is Apr so this will incur a 3 month delay overall. Even
then, the qualification (and hence spend of the 25k) would need to
be before this and hence in this FY; hence the need for the money now.
We might be able to gain back something like a month in the test period
by preparing better (we have three more months to do so) so as to have
a two month delay longer term, but overall it is clear we will be delayed
to some extent.
                              Cheers,
                               Paul