The Front-End Driver for the CMS Strip Tracker

The huge number of silicon strip channels (~11 Million) in the CMS Tracking Detector, makes reading out the analogue(10 bits) particle hit data a formidable challenge when triggering at 100 kHz. This equates roughly to 11 Terra bits/s of data which have to be read from the detector, processed and stored on disk. This feat of engineering will be accomplished by the The CMS Silicon Strip Tracker (SST) Front End Driver (FED), which has the unenviable task of reducing the data rate to ~ 100Mb/s at the back end of each FED. 450 FEDs in all will be used in the experiment.

The Front-End Driver module.

The FED is a 9U 400mm VME64x card that processes the raw data from 192 APV25 silicon readout ASICs, corresponding to 0.2% of the total tracker. After multiplexing and streaming, the data from the front-end are routed via analogue optical links to the FEDs. 96 optical channels are then digitised to 10bit precision at 40MHz and processed in large FPGAs, before being collated into events and sent to the CMS DAQ via either VME or the SLINK-64 protocol.

The FED receives optical signals from the tracker and converts, digitises and processes the data for onward transmission to the DAQ. The CMS system has no zero-suppression before the FED so the system is synchronous, and relatively easy to operate and debug, at the price of a high input data rate. The FED is now well into the manufacturing phase in a UK company with about 250 of the 500 production modules now in CERN; production should be complete by Q4 of 2006; the value of the contract is ~£2M.

The FED is a challenging board in terms of manufacturing, and cost, specifications. It is double-sided, with around 6000 components, and high component density. The 14-layer boards have almost 25000 tracks, serving 96 input channels (192 APV25s). The processing relies on the latest (at the time of design) FPGAs, and the many large parts require specialised assembly and inspection technology. It is equipped with unique custom analogue optical receiver modules, whose value is approximately equivalent to the remainder of the FED, so high quality in assembly (yield) and in handling are of paramount importance.

The Imperial College role has been to share the overall design, to develop certain crucial custom hardware, share testing and evaluation, and to provide DAQ software. Imperial FPGA expertise has increased rapidly in the last few years.

During 2004 and 2005 we wrote evaluation firmware, while base code was developed by RAL. The crucial front-end code originally written in Verilog at RAL was translated into VHDL at Imperial, with extra functionality to simulate CMS events. All testing software was written at Imperial, and systems installed at RAL and the manufacturers to verify quickly that modules are fully functional and identify faults. Although optical inputs cannot be tested during manufacture, all digital and most analogue functions can be validated on-site. Thus the effort of acceptance testing production modules, and reworking the inevitable fraction of faults is minimised; currently production yield is ~95%, and should be 100% after rework.

Page content provided by J. Fulcher.