The corresponding speaker for each talk is underlined (not supported by older browsers).
B. Bennetts
LogicVision
DFT (Design-For-Test) for electronic devices and systems has come a long way since its start in the 1960s, evolving from internal scan/ATPG through Boundary Scan and, now, Built-In Self Test. This presentation will re-visit the fundamentals of the three techniques, look briefly at what tools are available for BIST, and demonstrate current application through recent applications.
G. Chiaretti
Italtel
Silicon Optical Bench Technology is a Silica on Silicon based Technology able to hybridly integrate a variety of optical devices: passive components (splitters, WDM, filters...), active devices (laser, pin detectors), and both of them. After a review of this technology, its contributions to the CMS Tracker Optical Readout Link will be described. Mass production capability and the efforts needed to reach low cost link solutions will be discussed.
D. Gee
Hewlett Packard
This paper will show you how the business planning system works in Hewlett-Packard. It will introduce to you a ten step methodology for developing intermediate range plans as well as reviewing how to create and execute a breakthrough "Hoshin" plan. The importance of structured reviews and the overall integration of the various elements of the planning process will also be discussed.
George A. Riley
HyComp, Inc. Marlborough, MA, USA
As improved semiconductor device fabrication leads to ever faster, denser chips, interconnection has increasingly become the limitation to realizable chip performance. Entering this decade, semiconductor manufacturers routinely placed the chips of the nineties into the packages of the sixties. However, since then, many novel packages have been introduced, including more than a score of Òchip-scaleÓ packages. Beyond those packages, the growing commercial availability of several improved methods for flip chip interconnection now offers to the designer the possibility of the ultimate chip-scale package; the chip itself, the Òpackageless package.Ó
This paper elucidates several commercially available flip chip interconnection methods and describes their relative advantages and disadvantages from the user's perspective. Results and examples presented are based on HyComp's five years of trials and errors in designing, manufacturing, and testing chip-based flip chip hybrids and MCMs.
P. Smith
Matra-Marconi
Steve Watts
Brunel University
CERN's RD48 or ROSE (R&d On Silicon for future Experiments) Collaboration is investigating the radiation tolerance of silicon containing various impurities - oxygen, carbon, germanium and tin. The collaboration is concentrating on the problems of bulk damage with a clear objective of providing practical advice to the LHC experiments. There is now strong experimental evidence that more tolerant detectors can be made. Epitaxial material is found to be typically a factor two harder. Significant effects due to processing have also been seen. There have been many important advances in our understanding of bulk damage effects in silicon. The use of lower resistivity material is also an important issue that the HEP community needs to debate.
P. S. Winokur
Sandia National Laboratories
This presentation examines the role of commercial, radiation-tolerant, and radiation-hardened technology in high-energy accelerator applications. After a brief review of the radiation environment at the Large Hadron Collider, details of the design and manufacture of radiation-hardened microelectronics are given. The issue of availability of radiation-hardened ICs is discussed in light of a declining supplier base. Challenges associated with the use of commercial-off-the-shelf (COTS) technology in radiation environments are reviewed, including variability, qualification, and cost. A discussion of future technology trends is then provided in which susceptibility to total-dose and single-event phenomena are evaluated as technology scale toward submicron dimensions. The presentation ends with a discussion of Sandia National Laboratories strategy to meet its future needs for radiation-hardened microelectronics in defense and space applications.
W. Dabrowski a,b , F. Anghinolfi a ,
D. Campbell c , W. Gannon c , A. Grillo
d , P. Jarron a , J. Kaplon a,f , N.
Kundu g , D. LaMarra e , G. Meddeler
h , S. Picchiottino a , R. Szczygiel f
a CERN, Geneva, Switzerland
b Faculty of Physics and Nuclear Techniques, University of Mining and
Metallurgy, Cracow, Poland
c Rutherford Appleton Laboratory, Didcot, England
d Santa Cruz Institute for Particle Physics, UCSC Santa Cruz, CA,
USA
e University of Geneva, Switzerland
f Institute of Nuclear Physics, Cracow, Poland
g University of Oxford, Oxford, England
h NIKHEF, Amsterdam, The Netherlands
The binary readout architecture has been implemented in a single 128-channel chip using the DMILL technology. A prototype SCT128B chip has been manufactured successfully. It comprises all core blocks of the binary readout architecture: front-end, binary pipeline, derandomizing buffer as well as an internal calibration circuitry and an internal DAC for the discriminator threshold control. The ABCD chip is a development of the SCT128B which includes data compression and readout circuitry as defined by the SCT readout protocol. Test results on performance and radiation hardness of the SCT128B chip as well as the ABCD design will be presented.
V. Arbet-Engels*, G. Cervelli, K. Gill, R. Grabit, C.
Mommaert, G. Stefanini, F. Vasey
CERN, CH-1211, Geneva 23, Switzerland.
* corresponding author, e-mail: vincent.arbet.engels@cern.ch
tel: +41 22 767 8583
fax: +41 22 767 2800
Optical links for the CMS experiment are being developed for signal transfer from the front-end electronics of the tracker. The static and dynamic evaluation of one-way prototype analogue links has been performed. These links are based on representative optoelectronic components (edge-emitting lasers and pin-photodiodes) to be used in the future readout system. Characteristics of both transmitters and receivers and the full link transfer function are presented. The overall performance is discussed in terms of static and dynamic responses. Preliminary results on digital links are also discussed.
Authors: R. Baur, P. Ernst, G. Gramegna , M. Richter
Universitaet Heidelberg, Physikalisches Institut, Germany
We present the development of new front-end electronics suitable for a Time Projection Chamber (TPC). The front-end chain is comprised of two circuits: (i) A charge sensitive amplifier (CSA) with semi-Gaussian shaper and tail-cancellation. The CSA is matched to a 12pF pad capacitance. We measure an equivalent noise charge ENC of 230 e rms at Ts=650ns. The peaking time can be selected between 180ns-650ns. The tail suppression can be externally tuned to cancel tails between 0.1µs-1µs. (ii) A 16x256 cell switched capacitor array stores the input waveform at 14 MHz during the drift-time of the chamber. A 16 channel successive approximation ADC sequentially digitizes the signal at 1 MHz with 8-bit precision. Although the circuits are geared towards the CERES/NA45 TPC, the necessary flexibility to accomodate different operating conditions make it feasible for the ALICE experiment.
G Bohner, Jean Pierre Mendiburu
In this paper, I describe the method foreseen to process the electronic calibration of the crystal Electromagnetic Calorimeter of CMS. The analog and logic circuits being developped at LAPP for this purpose are described.
Vincent BONZOM, Laurent BLANQUART, Pierre DELPIERRE
CPPM/IN2P3, 163 Av de Luminy, CASE 907, 13288 Marseille Cedex 9,
FRANCE.
Peter FISCHER, Stephan MEUSER, Norbert WERMES
PHYSIKALISCHES INSTITUT, Nussallee 12, 53115 BONN, GERMANY.
Several pixel readout chips for the ATLAS experiment at LHC have been designed and tested. The chip architectures are described and measurements of the chip performance are presented.
The LEPTON Chip is a matrix of 12*63 pixels with a complete End Of Column decoder which has been designed by the CPPM group in DMILL radhard technology. It has been sucessfully operated after an irradiation of up to 30Mrad.
The Beer-and-Pastis Chip is a matrix of 12*63 pixels. It includes a tune threshold system in each pixel and delivers the Time Over Threshold information for analog purpose. It has been designed in AMS BiCMOS 0.8u in collaboration with the Bonn Physics Institute. These two chips have been bonded to detectors and successfuly tested in beam.
A front end demonstrator chip is under design (FE-A, common work BONN-CPPM). It includes 18 columns of 160 pixels and a complete control and readout circuitry. It will be used in the ATLAS module which uses 16 chips on one silicon sensor substrate.
J. Beringer, K. Borer, R.K. Mommsen
Laboratory for High Energy Physics, University of Bern, Switzerland
E. Monnier
Centre de Physique des Particules de Marseille, CPPM
IN2P3 et Universite d'Aix Marseille II, Marseille, France
R.B. Nickerson, A.R. Weidberg
Department of Nuclear Physics, Oxford University, UK
H.Q. Hou, K.L. Lear
Sandia National Laboratories, Albuquerque NM, USA
We present the final results of radiation hardness and life time studies of Light Emitting Diodes (LEDs) and Vertical Cavity Surface Emitting Laser diodes (VCSELs). About 250 LEDs from two different manufacturers and about 200 VCSELs produced by Sandia National Laboratories have been exposed to neutron and proton fluencies up to twice those expected at the inner tracker of ATLAS. We report on the radiation damage and the required conditions for its (partial) annealing, and we present post-irradiation failure rates of LEDs and VCSELs during several months of operation at increased temperature.
Summary prepared by M. Campbell, E. Cantatore, E.H.M.
Heijne and W.Snoeys
representing the RD19, WA97 and NA57 collaborations
ECP Division, CERN, Geneva, Switzerland
The development of a large area detector pixel system requires a significant effort beyond the single readout cell design. We will describe some of the problems we experienced and the solutions we applied to obtain a working and reliable pixel system for the WA97 experiment. These cover the assembly of the cells into a full readout chip, of readout chips and detector into a detector unit, and of different detector units onto a substrate to cover a large area. The development carried over several generations of readout chips. We feel the experience gained is essential in the development of working and reliable detector systems for LHC.
G.Cervelli*, C.Mommaert, V.Arbet-Engels, K.Gill, R.Grabit,
G.Stefanini, F.Vasey
CERN, CH 1211 Geneva 23, SWITZERLAND
The CMS tracker readout will make use of analogue optical links. In order to simulate and characterise their functionality within a complete readout chain, a software program has been developed in a LabVIEW environment. It allows for interchangeability of software modules and real hardware components in a transparent and modular way, so that both full software and mixed hardware/software simulation of the chain are possible. We present the characterisation of a full readout chain and a study of the readout chain specifications, based on Monte Carlo simulation techniques and statistical analysis of system parameters.
Corresponding author: Giovanni Darbo
INFN
Via Dodecaneso 33
I-16146 Genova Italy
eMail: darbo@genova.infn.it
Fax: +3910-353 6319
Tel.: +3910-353 6454
The System Architecture of the ATLAS pixel detector will be organized around 3 kind of chips: a front-end (FE) chip, a module controller chip (MCC) and a ladder controller chip (LCC). The FE chip has 3840 analog front-ends directly bump-bonded to the detector matrix and a back-end logic that does data sparsification and event time stamp. The MCC does event building, error handling and it has trigger and timing control logic. The LCC is the last chip in the chain and its function is the routing of event and control data from several MCC's to the off-detector electronics.
In the talk we describe the system architecture and we report on the its impact to the physic events. Some results from prototype chips will be also illustrated.
F. Corsi*, D. De Venuto+, V. Lenti^
* Department of Electrical and Electronics Engineering Polytechnic of
Bari, via Orabona, 4 70125 Bari, Italy, E-mail:
corsi@vaxba0.ba.infn.it
+ Faculty of Engineering, University of Lecce, via per Monteroni,
73100 Lecce, Italy E-mail: daniela@deeetr02.poliba.it
^ INFN and University of Bari, Italy
A new method to test the dynamic performances of analogue and mixed-signal integrated circuits is proposed, which is based on fault signature generation starting from the state space analysis of linear circuits.
By sampling the response of the circuit under test (CUT) to a simple rectangular pulse, a set of parameters alphas, functions of the circuit singularities, is evaluated, which constitute a signature for the CUT. Amplitudes perturbations of these parameters engendered by element drift failure, constitute a fault signature. The proposed testing procedure has been successfully applied to a typical analogue front end for direct readout of pixel detectors, which is generally constituted by a charge sensitive amplifier and shaper used in LHC experiments.
M. Dentan, P. Abbon, P. Borgeaud, E. Delagnes, N. Fourches,
D. Lachartre, F. Lugiez, B. Paul, M. Rouger;
CEA-DSM-DAPNIA Saclay, F-91191 Gif-sur-Yvette, France.
R. Truche, J.P. Blanc, O. Faynot, C. Leroux, E. Delevoye-Orsier,
JL. Pelloie, J. de Pontcharra;
CEA - Technologies Avancées - LETI, F-38054 Grenible Cedex 09,
France.
O. Flament, JM. Guebhard, JL. Leray, J. Montaron, O. Musseau, A.
Vitez;
CEA - Centre d'Etudes de Bruyères-le-Châtel, F-91680
Bruyères-le-Châtel, France.
L. Blanquart(1), V. Bonzom(1), P. Delpierre(1), R. Potheau(1), A.
Hrisoho(2);
IN2P3: (1) CPPM, F-13288 Marseille, France; (2) LAL, F-91405 Orsay
Cedex, France.
DMILL is a mixed analog-digital rad-hard (> 10 Mrads, > 1014 n/cm2) technology, which integrates, on an SOI substrate, 0.8 um CMOS, a vertical npn bipolar transistor and a P-type JFET. DMILL was developped by the CEA between 1990 and 1995. Its transfert to the industrial production line of TEMIC / Matra-MHS at Nantes (Fr.) started the end of 1995 and is now complete. This technology, which possesses exceptional features, is available for fabrication of prototypes, since April 1997 in the framework of MPCs organized by Europractice. DMILL will be available for mass production from October 1997.
W. Fallot-Burghardt, W. Hofmann, K.T. Knoepfle, E. Sexauer,
U. Trunk
Max-Planck-Institut fuer Kernphysik
M. Cuje, M. Feuerstack-Raible, F. Eisele, B. Glass, U.
Straumann
Universitaet Heidelberg
HELIX128S-2 is the second version of a 128 channel readout chip designed for the silicon vertex and the inner tracking microstrip gas chamber detectors of HERA-B; it has been manufactured in the AMS 0.8um CMOS process.A modified version (manufactured in the DMILL process) will meet thespecifications for the LHC-B vertex detector.
The analog signal path has been completely revised with the aimof enhanced noise, power and linearity behaviour; the readout speedwas increased to 40MHz. The bias generating part (formerly on an extra chip) has been included; all settings can be programmed via a serial interface.
HELIX128S-2 can store up to 8 events (formerly 4);the number of the pipeline column storing an event is transfered as trailer of the analog data to the output.
Measurement results will be presented as well as an irradiation test of the previous HELIX128 chip.
Peter Fischer
Physikalisches Institut, University Bonn, Germany
A prototype of a readout chip for multi channel detectors, like silicon strip detectors or MSGCs is presented. The chip accepts 128 digital input signals from a preamplifier / discriminator frontend at a rate of up to 80 MHz. The hit pattern is sparsified in real time and the addresses and event-ids of valid hits are stored temporarily in an on-chip FIFO. Multiple hits per event are possible. A trigger selection of interesting events can pick out only hits with a given event-id, all other hits are automatically discarded. The chip size of the presented architecture depends on the required multiplicity and on the data rate, but not directly on the trigger delay.
K. Gill*, V. Arbet-Engels, G. Cervelli, R. Grabit, C.
Mommaert, G. Stefanini, F. Vasey
CERN, CH-1211, Geneve 23, Switzerland.
J. Troska
Blackett Laboratory, Imperial College, London SW7 2BZ, England.
* corresponding author, e-mail: gill@vxcern.cern.ch
As part of the development of optical links for readout of the CMS tracking detectors, 1300 nm multi-quantum-well edge-emitting lasers and InGaAs p-i-n photodiodes have been irradiated with neutrons and 60Co-gammas. Results are presented for the radiation induced changes in laser threshold, slope-efficiency, linearity, signal-to-noise ratio, and p-i-n diode leakage current and responsivity. Based on a parameterisation of the damage effects, the damage expected under realistic LHC operating conditions is estimated. Progress and results from laser reliability studies are also presented.
Dachs(1*), F. Faccio(1), A. Giraldo(2), E. Heijne(1),
Jarron(1), K. Kloukinas(1), A. Marchioro(1), A. Paccagnella(2)
(1) CERN, 1211 Geneva 23, Switzerland
(2) University of Padova - INFN Padova, via Marzolo 8, I-35131
Padova, Italy
* On leave from University of Montpellier, France
Commercial submicron VLSI technologies are potentially interesting also for applications in regions of the LHC experiments where moderate radiation resistance is required. As in such regions the total dose will be accumulated over a period of 10 years, and as the machine will not operate continuously, the dose rate will be low.
In this work, we present the results of a low dose rate irradiation (0.15 krad(Si)/h) on MOS transistors in two different commercial submicron processes (0.5um CMOS and 0.8um BiCMOS). The transistors have been irradiated up to 60 krad(Si) over a period of 11 weeks in discontinuous steps of 15 hours.
A. Goldsher, V. Kucherskiy, V. Mashkova
State Scientific Research Institute Pulsar,
Okruzhnoy proyezd, 27, Moscow, Russia
The matters of designing and manufacturing an application specific semicustom array (ASSA), intended for building on its basis of an eight-channel front-end LSIC have been considered. In the capacity of the ASSA's active components there have been used n-p-n transistor structures, including ones with Schottky diodes, having a unity-gain frequency fug about 7 GHz, p-n-p vertical transistors with collectors in substrate. Passive components are resistors (high- and low-ohmic) and capacitors based on MOS structures. The ASSA contains over 7000 components, among them 1400 transistors. On the basis of this ASSA, together with the specialists of the MEPhI Electronics department, there are being conducted the works on the creation of several LSIC types for application in physical experiments within the programs of the leading Russian and foreign scientific centers.
G.P. Grim, R.L. Lander
UC Davis
Results from tests of a sparsified pixel readout chip, (SPARC) will be presented. The ASIC is an 8 column by 120 row array of 48 µm x192 µm pixel unit cells, with each cell containing an analog front-end with pulse height discrimination for signals down to 1500 e-'s at the LHC, noise of less than 100 e-'s ENC, leakage current sink, neighbor logic, and pixel mask. Readout is accomplished using a column based readout scheme employing a simple inter-column token for bus arbitration, a current mode data bus for both analog and digital data, and end of column time stamp buffering . The SPARC chip has been laid out and fabricated in the HP 0.5 µm process.
Supported by U.S. DOE.
L. HEBRARD, J.P. BLONDE, M. AYACHI, Y. HU, G. DEPTUCH, W.
KUCEWICZ
Laboratoire d'Electronique et de Physique des Systèmes
Instrumentaux
LEPSI
IN2P3-CNRS/ULP Strasbourg
France
J.P. COFFIN, F. JUNDT, C. KUHN, J.R. LUTZ
Institut de Recherche Subatomiques
IReS
IN2P3-CNRS/ULP Strasbourg
France
The circuit described here is designed to fulfill the requirements of the readout electronics for the Silicon Strip Detectors (SSD) of the ALICE experiment. It is a 128 channels chip. Each channel amplifies, shapes and stores as a voltage signal the charge deposited on a strip of the detector. An analog multiplexer allows a sequential readout of the data through an output buffer shared by the 128 channels. A slow control mechanism is used to bias accurately the different analog blocks and to control the shaping time and a test pulse generator. The relevant specifications are given in the summary.
C. Dachs(1), F. Faccio(1), A.Giraldo(2), E. Heijne(1), P.
Jarron(1), A. Marchioro(1), E. Noah?, A. Paccagnella(2)
1) CERN-ECP
2) University of Padova
An investigation of the total dose behaviour of three different commercial submicron technologies has been carried out. Existing reports on such technologies and a set of theoretical studies have reported that such technologies will become more immune to total dose effects, mainly through the introduction of very thin gate oxides. We present a set of comparative measurements carried out on test structures irradiated up to 1 Mrad (SiO2) in 0.5, 0.35 and 0.25 um CMOS conventional transistors and also on special "enclosed" structures, laid out to overcome leakage current problems. The results obtained so far are very encouraging and substantially confirm the expected trends; very low voltage shifts have been measured; the new layout techniques applied, despite an increase in area used, also shown an effective technique to solve leakage current problems.
Christophe de La Taille, V. Radeka
At the beginning of this year, most decisions have been taken on the front end electronics of the ATLAS liquid argon calorimeter and have been written in the Technical Design Report. The talk will review briefly the various elements of the front-end : calibration, preamps, shapers... from the point of view of design, measured performance and implementation.
S. T. Liu and T. Bradow
Honeywell Solid State Electronics CenterPlymouth, MN 55441, U. S. A.
This paper describes radiation response/performance of a further hardenedCMOS technology by characterization of the threshold voltage shifts andleakage currents as a function of total dose. The threshold voltage shiftsof the top channels were less than 170 mV at 50 Mrad for both NMOS and PMOStransistors. No radiation induced leakage currents were observed over theentire range of radiation test (100 Krad to 50 Mrad). This data furtherdemonstrates the suitability of this technology for LHC experiments.
K. Kloukinas, C. Ljuslin, A. Marchioro, P. Moreira, G.
Stefanini, F. Vasey
CERN/ECP-MIC
All complex data acquisition systems such as those which will be used for the LHC experiments require not only a data path for the read-out of analog or digital data, but also fairly sophisticated so called ìslow control systemsî for the more mundane functions, such as control of the status of the detector, front end calibrations, monitoring of environmental parameters, downloading of parameters and distribution of critical timing information and their adjustments.This paper describes the architectural design of such a system optimized for the CMS inner tracker detector. This design was constrained by the heavy demand on reliability, radiation hardness, cost and minimization of number of different types of components. The resulting design is a careful mix of a long distance optical network with a local electrical network. The architecture, functionality, protocols and some of the key components used in these networks will be described.
O.Martin, B. Dinkespiler, M. Jevaud, C. Olivetto,
E.Monnier, M.Wielers, S. Tisserant
Centre de Physique des Particules de Marseille, CPPM
IN2P3-CNRS et Université d'Aix-Marseille II, Marseille, France
M.L Andrieux, J. Ballon, J. Collot, A. Patti
Institut des Sciences Nucléaires, ISN
IN2P3-CNRS et Université de Grenoble I, Grenoble, France
L.O. Eek, A. Go, B. Lund-Jensen, M. Pearce, J. Söderqvist
Royal Institute of Technology, KTH,
Physics Dept. Frescati, Stockholm, Sweden
J.P. Coulon
Laboratoire de l'Accélérateur Linéaire, LAL
IN2P3-CNRS et Université de Paris XI, Orsay, France
Our group has been concentrating its efforts in the last years [1] [2] on analogue optical solutions to the read-out requirements of the ATLAS liquid argon electromagnetic calorimeter. We now present results from a demonstrator of a 64 channel analogue optical link.
Signals from outside the calorimeter cryostat must be transmitted to the counting room 70 metres away with a 10-bit dynamic range and minimal power consumption.
Arrays of VCSEL diodes, already known [3] as reliable in terms of radiation hardness and life time, are used as emitters. The receiver is based around a custom-designed PIN photodiode array. Thorough laboratory tests of the entire demonstrator link are discussed.
P.O'Connor*, G. Gramegna+, P. Rehak*, F. Corsi+, C.
Marzocca*
* Brookhaven National Laboratory, Upton, NY 11973 USA
+ Politecnico di Bari, Dipartimento di Elettrotecnica ed Elettronica,
via E. Orabona 4, 70125 Bari, Italy
An ultra low noise preamplifier for small capacitance (200fF), low leakage current solid state detectors has been designed and fabricated in two different CMOS technologies. The circuit is suitable for application in X-ray detection systems and its performances in terms of gain linearity and equivalent input noise charge (ENC) compare favourably with present state-of-art circuits. A linearity error less than 0.1% up to 1.8fC input charge and an ENC of 13e- rms at 2.4us shaping time have been achieved by adopting original circuit solutions for the feedback scheme of the charge sensitive amplifier, which has been realized with a P-channel MOSFET biased in the weak inversion region. One of the two version of the circuit include also an integrated shaper realized by a MOSFET-C approach. The general philosophy of the circuit along with the main experimental achievements will be reported in the paper.
A.Holmes-Seidle, J.Matheson, S.Watts
Brunel University, Uxbridge UB8 3PH
G.Hall, M.Millmore, M.Raymond
Imperial College, London SW7 2BZ
APV6 chips have been gamma irradiated using a 60Co source in order to confirm the radiation hardness expected from measurements on individual transistors and on the APV5 chip. The additional capabilities of the APV6 are outlined, the test system described and detailed measurements are presented of noise, power consumption and pulse shape following irradiations of up to 15 Mrad. We believe that full functionality of the chip will be preserved under LHC operating conditions.
P. Moreira, T. Vaaraniemi, A. Marchioro and T. Toifl
An ASIC consisting of an array of four linear laser drivers has been designed, fabricated and tested. The IC is dedicated to the transmission of analogue data from two of the CMS central tracker detectors to the front-end digitizer cards.
The ASIC drives a laser diode converting the analogue data produced by the front-end APV chip into an amplitude modulated optical signal. Each driver contains a programmable current source allowing independent biasing of any of the four laser diodes in its linear region of operation. The laser driver was designed in an 0.8µm BiCMOS process. The driver has been successfully tested both electrically and in combination with a laser diode/optical receiver. Measurement results are reported.
Christian Neyer
GSI Darmstadt/Germany e-mail: C.Neyer@gsi.de
A discriminator for precise time measurements has been integrated in a bipolar chip. It works with two thresholds and finds the beginning of a pulse by linearly extrapolating the leading edge. This is used for compensating fluctuations of the pulse shape. The remaining walk at the output is 30 ps peak to peak when the rise time at the input is varied between 250ps and 1ns. For amplitudes between 50mV and 250 mV, this is 40 ps peak to peak. A chip of this kind is foreseen for Time of Flight measurements in ALICE.
S. Panebianco, V. Russo, S. Reito
Dipartimento di Fisica dell' Universita' and Sezione INFN, Catania,
Italy
Two full custom Analog Memories have been designed, realised and now are under test. These Memories have been realised in view of the final design of the readout system for the Silicon Drift Detectors (SDDs) that will be used at LHC in ALICE detector as part of the Inner Tracker.
The two memories have been integrated in double poly, double metal AMS 0.8 un CMOS. The memories have input and output swings of 3 V, a linearity better than 0.1% and a pedestal variation from cell to cell less than 1 mV.
James L. Pinfold
University of Alberta.
A brief introduction to the ATLAS liquid Argon Calorimetry Switched Capacitor Array readout system downstream of the shaper chips will be given. The talk will concentrate on the development of a Field Programmable Gate Array implementation of the SCA Pipeline Controller that enables the SCA readout system to function as an essentially deadtimeless Random Access Analog Memory. The system prototyped so far is capable at running in excess of 40 MHZ - in accordance with LHC requirements.
A. Marchioro - CERN/ECP-MIC, marchior@sunvlsi.cern.ch
P. Moreira - CERN/ECP-MIC, pmoreira@sunvlsi.cern.ch
P. Placidi - CERN/ECP and University of Perugia,
placidi@sunvlsi.cern.ch
The CMS central tracker will use clock and trigger signals derived from the general Timing and Trigger Control (TTC) system developed within the RD-12 project. These signals are transmitted encoded in a 40 MHz square wave that simply presents a missing pulse when a trigger occurs.This paper describes the design of a dedicated low jitter PLL-Delay ASIC optimized for this application. Design requirements and preliminary simulation results are reported. Special emphasis is put into the optimization of several blocks of the PLL; furthermore the description of a mathematical model used for the optimization of the circuit is detailed.
M.French, L.L.Jones, P.Murray
Rutherford Appleton Lab, UK
M.Raymond, G.Hall
Imperial College London, UK
The APV6 is the final prototype of the rad-hard 128 channel front end readout chip for the CMS silicon tracker at LHC, fabricated in the Harris AVLSIRA process. Each channel comprises a low noise amplifier, a 160 cell analogue pipeline and a further signal processing stage which can implement a deconvolution operation to achieve single bunch crossing time resolution. The data from all channels is transmitted on a single serial output via a high speed analogue multiplexer. The chip incorporates necessary system features, including on-chip bias and calibration pulse generation.
G. Mazza
INFN sezione di Torino, Italy
A. Rivetti
Politecnico di Torino, Italy
We present two schemes for 2-stage transimpedance amplifier based on the active feedback principle. The first one is a current amplifier followed by a transimpedance amplifier. The second one is a transimpedance amplifier followed by a voltage amplifier. Both schemes can achieve a gain of 2-4 M½ with around 8 -18 Mhz of bandwith. The circuits perform a square root signal compression in order to reduce the A/D converter dynamic range without decreasing the signal-to-noise ratio.
D.B. Kerwin, J.M. Benedetto, R.R.L. Sharman
UTMC Microelectronic Systems
4350 Centennial Blvd.
Colorado Springs, CO 80907
UTMC Microelectronic Systems has developed two radiation hardened process modules for hardening commercial CMOS processes and has demonstrated the effectiveness of these approaches at three different commercial foundries. UTMC Microelectronic Systems' Commercial RadHardTM technology using American Microsystems, Inc. (AMI) 0.6 micron commercial CMOS process achieves threshold voltage shifts of < 1 mV/krad(Si), with intra-device leakage well controlled to total dose levels exceeding 200 krad(Si). Inter-device leakage exceeds 150 krad(Si) requirements for UTMC Microelectronic Systems' 0.6 micron gate array family. UTMC Microelectronic Systems provides Commercial RadHard TM products that can be fully qualified (using MIL-STD-883, Method 1019) to a 100 krad(Si) radiation hardness assurance conformance level (RHACL), at a reasonable cost by using commercial CMOS processes.
Jim Swonger
Harris Semiconductor
Melbourne, Florida, USA 32902-0883
Signal processing electronics for front-end applications operates in difficult radiation environments, and hardened parts are required for reliable long-term operation. Hardened processes and parts have evolved over years of R & D and have been produced in prototype quantities. The large experiments now under development will increase the number of data channels by orders of magnitude, forcing manufacturing, procurement and assembly methods. Unless these improved methods are adopted, affordable systems will not be possible.
In this paper, we describe the use of Qualified Manufacturers List (QML) methodology to the production of hardened parts at Harris. The use of QML contrasts sharply with earlier procurement practices, most of which depended on rigorous controls over the manufacturer's procedures. It replaces these controls with the vendor's own commercial best practices allowing the specialized components to be built using the same facilities as commercial parts. With the strong reduction in demand for military parts in the US and other countries, this was a neccessary approach if qualified sources were to be available at all.
Renato TURCHETTA
LEPSI (CNRS/University)
23, rue du Loess
F-67037 Strasbourg Cedex
A CMOS mixed analog-digital circuit (APVD) for the silicon tracker in CMS has been designed in the radiation hard technology DMILL. This circuit is pin-to-pin compatible to the APV6, fabricated in a radiation hard process by Harris Semiconductor.
The APVD has been designed within a French-British collaboration of several laboratories: CEA-DAPNIA, IPN, IReS, LEPSI and RAL.
The design as well as the expected performances will be presented in this paper
F. Vasey, V. Arbet-Engels, G. Cervelli, K. Gill, R. Grabit,
C. Mommaert, G. Stefanini
CERN, Geneva (Switzerland)
We present the concepts underlying the development of a rad-hard optical link based on edge-emitting laser transmitters, single-mode optical fibre ribbons, multi-way MT connectors and pin-photodiode receivers operating at a wavelength of 1300nm. One-way transmitter- and receiver-building blocks, assembled using silicon waferboard technology, allow for high flexibility and modularity in the system design. This is illustrated by reviewing both the analogue-readout and digital-control optical systems of the CMS tracker, which are based on identical optoelectronic components. Ongoing developments and timescales to production are discussed.
A Weidberg
Optical links are being developed for the ATLAS SemiConductor Tracker. The links are based on radiation tolerant LED-fibre-PIN diodes. The links are used to transfer data off the detector and to receive all the trigger timing and control data required to operate the SCT modules. In order to minimise the number of links, the bunch crossing clock and the trigger and control data are multiplexed onto one fibre. Results on system tests are combined with irradiation data to verify the suitability of the system for 10 years operation at LHC. First results on the front end chips driver and demultipliexing chip are also presented.
P. Bailly(1), C. Beigbeder(2) , R. Bernier(2) , Zhang Bo(1), D.
Breton (2), G. Bonneaud(3),T. Caceres(2) , P. Cros(2), R. Chase(2),
J. Chauveau(1), L. DelBuono(1), F. Dohou(3), A. Ducorps (2), F.
Gastaldi(3), J.F. Genat(1), A. Hrisoho(2), P. Imbert(2), H.
Lebbolo(1), P.Matricon(3), C. Renard(3), L. Roos(1), G. Oxoby(4), S.
Sen(2), C. Thiebaux(3), K. Truong(2), G. Vasileiadis(3), M.
Verderi(3) , J. Va'avra(4), D. Warner(5), R.J. Wilson(5), G.
Wormser(2), F. Zomer(2)
(1) LPNHE, Univ. Paris 6 et 7, 75252 Paris Cedex France
(2) LAL Orsay, 91405 Orsay, France
(3) X-PHNE, Ecole Polytechnique, Route de Saclay, 91128 Palaiseau
Cedex France
(4) SLAC, Stanford University, PO 4349 Stanford CA94309, USA
(5) Colorado State University, Fort Collins, CO 80523 , USA
The DIRC front-end electronics chain for the BABAR experiment is presented. Its aim is to measure to better than 1 ns the arrival time of Cerenkov photoelectrons, detected in a 11,000 phototubes array and their amplitude spectra. It mainly comprises 64-channel boards (DFB) equipped with 8 ASIC VLSI full custom analog chips, performing zero-cross discrimination with 2 mV threshold and shaping, 4 ASIC VLSI full custom TDC chips, performing timing measurements with 500 ps binning and a readout logic selecting hits in the trigger window, and crate controller cards (DCC) serializing the data collected from up to 16 DFBs onto a 1.2 Gb/s optical link. Extensive test results of pre-production units will be presented.
Yasuo Arai
KEK, National High Energy Accelerator Research Organization
Institute of Particle and Nuclear Studies
yasuo.arai@kek.jp
and
Jorgen Christiansen
CERN, ECP/MIC
christia@sunvlsi.cern.ch
The architecture of a new integrated TDC has been studied for the ATLAS precision muon tracker. A data driven architecture using several levels of buffering have been chosen to obtain a flexible solution using the minimum amount of silicon area. Intensive simulation studies have been performed to verify its correct function under different working conditions. Matching of hits to triggers are based on time tags. Matched hits are read out on a shared 80 Mbits/s serial link. First series of prototype chips are planned for the end of 1997.
M.Bercher, P.Busson, L.Faurlini, D. Lecouturier
The CMS level-1 trigger system will be able to retain interesting physics signal with good efficiency while rejecting background events from QCD. In order to achieve a high rejection power the electron/photon trigger algorithm involves both isolation cuts and longitudinal and transversal cluster shape analysis. The transversal cluster shape analysis is performed at the digital front-end level by a dedicated circuit working in pipe-line mode at 40 MHz. We report about the design of this circuit and the performances of a prototype already implemented in a field programmable gate array.
Ian Brawn, Alain Corre, Nick Ellis, Philippe Farthouat,
Georges Schuler
CERN
The ATLAS level-1 Central Trigger Processor (CTP) will correlate sub-triggerresults and form the global level-1 trigger decision. It will be implemented as a fully synchronous, 40 MHz pipeline processor. To evaluate the proposed CTP design, a demonstrator module has been built. This module implements all of the core functionality foreseen for the final system, but processes only one quarter of the data (32 input signals rather 128). Extensive use is made of FPGAs. The demonstrator has a latency of 2.5 bunch crossings. Presented here are the CTP demonstrator design, the software used to handle the demonstrator, and the results of beam tests with the demonstrator.
R.E. Breedon, H. Cooper, B. Holbrook, Winston Ko, P.
Murray, G. Song, C. Thanh
University of California, Davis, CA, USA
A switched capacitor array (SCA) will provide analogue storage for the cathode readout of the cathode strip chambers in the CMS endcap muon system. After a series of smaller prototypes, the first iteration of the full sized 16-channel, 96-cell per channel SCA is undergoing precision testing using a specially designed test board. As a result of several innovative design features, the chip exhibits a remarkably low level of cell-to-cell pedestal fluctuation. The system control and integration of the SCA, and test results including linearity, cross-talk, pedestal variation and other dynamic effects will be presented.
Jorgen Christiansen
CERN/ECP - MIC
1211 geneva 23
phone: +41 22 767 5824
Fax: +41 22 767 3394
Email: jorgen.christiansen@cern.ch
A 32 channel data driven Time to Digital Converter (TDC) has been implemented as an integrated circuit with an area of 34mm^2 in a 0.7um CMOS process. The time conversion is performed by storing the state of a Delay Locked Loop and a 16 bit counter. A two words deep de-randomizing buffer per channel is used before a common 256 hits deep level 1 buffer. Data from the l1 buffer are optionally matched to a trigger. Matching hits are stored in a 32 words deep read-out FIFO. At 40MHz the absolute RMS error of the TDC is 0.29ns.
A. Connors, J. Garvey, S. Hillier, D. Rees, R. Staley, P. Watkins,
A. Watson
School of Physics and Space Research, University of Birmingham, UK
E. Eisenhandler, M. Landon, J.M. Pentney
Queen Mary and Westfield College, University of London, UK
J. Edwards, C.N.P. Gee, A.R. Gillman, R. Hatley, T.P. Shah, V.J.
Perera
Rutherford Appleton Laboratory, UK
The core of the ATLAS level-1 calorimeter trigger system is the electromagnetic cluster-finding algorithm implemented in ASICs. The algorithm demands a high level of data fanout between modules containing the ASICs, which will be achieved by data transport at 160 Mbit/s across point-to-point transmission-line crate backplanes.
To prove the viability of this technique a small-scale backplane has been constructed, allowing data communication between nine cluster-processing modules in a demonstrator system installed at the ATLAS test-beam at CERN.
We present here some measurements of data crosstalk and bit-error rates.
A. Connors, J. Garvey, S. Hillier, D. Rees, R. ;Staley, P.
Watkins, A. Watson
School of Physics and Space Research, University of Birmingham, UK
I. Brawn, N. Ellis, P. Farthouat, G. Schuler
CERN, Geneva, Switzerland
P. Hanke, E.E. Kluge, A. Mass, K. Meier, U. Pfeiffer, C.
Schumacher
Institut für Hochenergiephysik der Universität Heidelberg,
Heidelberg, Germany
E. Eisenhandler, M. Landon, J.M. Pentney
Queen Mary and Westfield College, University of London, UK
J. Edwards, C.N.P. Gee, A.R. Gillman, R. Hatley, T.P. Shah, V.J.
Perera
Rutherford Appleton Laboratory, UK
C. Bohm, M. Engström, S. Hellman, S-O. Holmgren, S.
Silverman, N. Yamdagni, X. Zhao
Physics Department, University of Stockholm , Stockholm, Sweden
The ATLAS level-1 calorimeter trigger system relies upon several key technologies which have been tested in a demonstrator programme. Operating with signals from prototype ATLAS calorimeters, the final phase of this programme has evaluated some critical aspects of high-speed data transmission, including 1.6 Gbaud electrical links and data fan-out on crate backplanes at 160 Mbit/s. Several trigger sub-systems have been interconnected for the first time to form a slice of the ATLAS level-1 trigger.
We present here some results from the operation of this demonstrator system in the ATLAS test-beam at CERN.
J. Ero, T. Ladzinski, N. Lejeune
CERN Div. ECP
The Dual PCI Input-Output Processor is a board developed for the CMS DAQ. The i960RP type embedded processor has direct access to two separate PCI buses, can act as bridge between them. The board can be inserted between the CMS-RDPM and the link controller interface boards. It establishes a fast control of the Link Interfaces increasing the readout speed. It gives a possibility to perform check tasks and certain level of data compression. Equipped with an RT Operating System it becomes the kernel of a simple local Data Acquisition System, which has an application field at the beam tests.
D. Francis
A prototyping effort for a small scale yet fully functional vertical slice of the ATLAS DAQ system is ongoing since early 1996. The Read-Out crate is the modular element sitting between detector front-end electronics and the event builder. The current architecture and organisation of the Read-Out crate is presented. A prototype implementation of the Read-Out crate based on technology embedded in VME is described. The performance assessment, based on a detailed series of measurements, of the current protoype implementation will be discussed.
A Fucci
CERN/ECP
High speed data buffering is required at different levels in the readout chain of LHC experiments. The basic data acquisition unit for all sub-detector readout systems is expected to be a programmable, message-driven, multi-port memory (DPM) with high throughput (>100 MB/s) and high capacity (>100 MBytes). Moreover, during the present phase of design and evaluation of readout components, dual port memories are the basic test tools to generate and acquire data to/from a high speed digital system such as a front-end readout or event builder switch. CMS is developing a series of DPM modules for applications ranging from testing, in realistic LHC conditions, the event building architecture to final data acquisition systems.
Diminique GIGI
CERN ECP-CMD
All the present RDPM prototypes are implemented in 6U-VME boards. They contain all the necessary control logic for two independent PCI busses.
The VME bus is also used as the readout bus, hence the RDPM has a programmable VME-DMA controller, capable of multiDMA sparse readout at about 60 MB/s.
The logic implementation uses FPGA circuits of XILINX or ALTERA technology.
The dual port memory module is a PMC-PCI board of either 8MB static or 32 MB dynamic RAM, and about 400 MB/s bandwidth.
The output PCI bus is build around a list processor engine that should be able to drive ATM , FB and other PMC-PCI link protocols Four prototype boards are currently in use in various test environment including links to personal workstations.
Rob Halsall
Rutherford Appleton Laboratory
The CMS tracker Front End Driver (FED) prototype is a technology demonstrator which when fully configured is capable of receiving, digitising & processing the data from 64 optical fibres carrying the analogue data frames from 128 front end chips. At this density of optical channels around 700 FEDs occupying 50 Crates will be required in the counting house to process the data from 12 million detector channels in the CMS micro strip tracker.
The prototype, implemented as a 9U by 400mm VIPA compatible VME bus module, receives 64 of these optical signals, converts them to electrical levels and then digitises with 64, 10 Bit at 40 MHz, Analogue to Digital Converters (ADCs). This is then followed by Field Programmable Gate Array (FPGA) based Digital Signal Processing (DSP) which at 100 kHz First Level Trigger (FLT) rate extracts around 50 M bytes/s per percentage occupancy of hit data from the 1.6 G byte/s of digitised analogue data streams input to each FED.
The FERMI Collaboration
Presented by Magnus Hansen, CERN/ECP
The activity in the FERMI collaboration has during the last two years been concentrated on providing architectures that fulfill the requirements set by the interested experiments in the domain of calorimeter readout. Currently, FERMI is being implemented on all calorimetric detectors in CMS, and is the baseline for the ATLAS Tiles calorimeter prototype.
As a consequence, new digital ASICs are being developed in line with the final requirements, including optimisation and simplification of almost all functional units.
The current status of the project is described, together with the most recent performance results from beam tests on different calorimeter prototypes. Excellent results, both in terms of energy resolution and trigger feature extraction performance, fulfilling the requirements of the detectors, are provided.
R.Halsall, W.J. Haynes et al
Rutherford Appleton Laboratory, UK
The CMS detector at LHC will contain over 12 million electronic channels, with most assigned to silicon and MSGC tracker devices. On-detector ASICs will be read out into the Data Acquisition System (DAQ) via Front-End Driver (FED) receiver electronics.
This paper will discuss the evolution of the tracker Front End Driver for CMS with consideration of a common FED base module approach for all subdetectors. Such a FED might be based on a standard (VIPA) 9U by 400mm base module with up to 8 slots for PCI Mezzanine Cards (PMCs). Detector-dependent PMCs would be used to customise the FED for a specific subdetector with the base module providing all the common DAQ services such as Timing, Trigger and Control (TTC) with fast data links to the DAQ and Computer infrastructure.
Presented by Greg Heath, University of Bristol, UK.
The design of the Level 1 calorimeter trigger system for CMS will bepresented. CMS plans to trigger mainly on electron and photoncandidates, jets and missing transverse energy, and combinations ofthese, as well as muon chamber signals. The calorimeter triggerprocessing takes place in three stages: primitive extraction, featurerecognition and feature sorting. All processing is performed in fullysynchronous, deadtimeless pipelines clocked at the LHC frequency of 40MHz, or multiples thereof. The status of design and prototyping work forall stages of the processing will be reviewed. The development of afast, pipelined sort algorithm for the later stages of the processingwill be described.
Tomasz Ladzinski, Dirk Samyn
CERN - ECP/CMD
The proposed CMS data acquisition system will be built around a central switching unit. A methodical study of data links and event building performance is therefore a crucial point in the development of the readout system. A modular OO software environment for testing CMS DAQ prototypes is presented. Results of point to point link tests of various technologies obtained in test setup environment are further shown. A short overview of event building aspects is given, together with a more detailed description of test bed assembled out of custom (CMS-RDPM) and commercial(Fibre Channel/ATM) products. The most recent results from the ongoing activities in the field of event building will be presented.
corresponding author Paolo Morettini
We present second level trigger for the ATLAS experiment based on the pixel vertex detector. This trigger is designed to tag individualb-jets on the basis of the presence of tracks having large impact parameters to the primary vertex. Moreover, it can allow the detection of secondary vertexes and the evaluation of their invariant mass.
M. Mota
LIP, Lisboa / CERN, Geneva
J. Christiansen
CERN, Geneva
A 4 channel, self-calibrating, High Resolution Time to Digital Converter with an RMS error below 49 ps over a dynamic range of 3.2 us has been developed. Its architecture is based on an array of delay locked loops and a 8 bit coarse time counter driven by a 80 MHz reference clock. Time measurements are buffered in two time registers per channel followed by a common 32 words deep read-out FIFO. The HRTDC has been built in a 0.7 um CMOS process using 21.6 mm^2 of silicon area.
D Myers
CERN/ECP
Whilst in the past a certain amount of duplication took place between experiments the reduction in funding and staff will impose improved use of resources for LHC. In particular, it can be argued that there are no technical reasons why the four experiments need to have independently-developed control systems. However, if care is not taken one can end up with incompatible control systems for each sub-detector within a single experiment. This paper considers the issues which must be tackled in order to avoid such a Tower of Babel.
C.Bacci, F.Ceradini, G.Ciapetti, F.Lacava, A. Nisati,
E Petrolo, L.Pontecorvo, S.Veneziano, L.Zanello
INFN Sezione di Roma,
Universita' di Roma La Sapienza and Universita' di Roma3, Rome Italy
R.Cardarelli, A. Di Ciaccio, R.Santonico
INFN Sezione di Roma2,
Universita' di Roma Torvergata, Rome Italy
We present the design and implementation of the first level muon trigger in the barrel region of ATLAS. The trigger is based on the use of a dedicated fast, finely segmented gaseous strip detector (RPC), Resistive Plate Chamber, to unambiguously identify the interaction bunch crossing and to provide a sharp threshold over a large interval of transverse momentum. The transverse momentum selection is done with a fast coincidence between strips on different planes, whose number is defined by the need to minimize the rate of accidental coincidences. The different momentum selection criteria required by the relevant physics processes, are met using low-pT and high- pT trigger. The trigger logic is done with a coincidence matrix circuit, based on a dedicated ASIC.
I. Brawn, A. Connors, J. Garvey, S. Hillier, D. Rees, R. Staley,
A. Watson
University of Birmingham, UK
C. Geweniger, P. Hanke, E. Kluge, A. Mass, K. Meier, U.
Pfeiffer, A. Putzer, K. Schmitt, C. Schumacher, K. Tittel, M.
Wunsch
Institut für Hochenergiephysik der Universität Heidelberg
E. Eisenhandler, M. Landon, J.M. Pentney
Queen Mary and Westfield College, University of London, UK
J. Edwards, C.N.P. Gee, A.R. Gillman, R. Hatley, J.L. Leake, G.C.
Lewis, T.P. Shah, V.J. Perera
Rutherford Appleton Laboratory, UK
This paper describes the design and the programming of a Front-End Module (FEM) for the first-level trigger, which is part of a demonstrator program to test and harden design techniques applied to high-speed data transmissions, Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs). The programming of the module is one step closer to the final ATLAS trigger system where calorimeter trigger tower data from a bunch crossing that generates a level-1 accept signal must be captured at run time for recording. We present here results from the operating of this Front-End Module in the demonstrator system installed in the ATLAS test-beam at CERN.
Maciej Gorski a), Ignacy M. Kudla a), Krzysztof T. Pozniak
b)
a) Warsaw University, Institute of Experimental Physics, Hoza69,
00-681 Warsaw, Poland (kudla@hozavx.fuw.edu.pl)
b) Warsaw University of Technology, Nowowiejska 15/16,
00-665 Warsaw, Poland (pozniak@vxdesy.desy.de)
The CMS detector will have a dedicated subdetector (RPC chambers) to identify muons, measure their transverse momenta pt, and determine the bunch crossing from which they originate. Trigger algorithm is based on muon track search and classification in raw data from the RPC chambers. A huge interconnection network is needed to fulfil this task. It can be built in the control room only, far away from the detector.
To reduce the cost of the links transmitting data from the detector to the control room, a compression/decompression system is proposed. Only the non zero RPC data are sent via this system. The idea of such a system and its limitations are discussed. High Speed Data Transmission and Compression for the CMS RPC Muon Trigger
A. RACZ
CERN
The logical model of the CMS front-end readout chain is described in a behavioural way. Although all the sub-detectors are intrinsically different, they must all obey to a common logical description. Then this conceptual harmony can be extended to the physical implementation. Such a standard approach is valuable during all the life time of the experiment from early design specifications up to final integration and maintenance. In the intermediate phase of prototyping, VME is used as the front-end readout bus. For maximum performances, a hardware programmable sequencer has been developed to move data over the bus : its capabilities are presented.
J.F. Renardy
The calibration of the Atlas liquid argon calorimeter requires a test pulse command finely adjustable with respect to the local 40MHz clock. The present TTC system has not foreseen such a requirement. This paper describes one solution to implement the needed signals with a standard TTC receiver chip and presents the performances obtained.
Werner Riegler (CERN)
For the ATLAS MDT electronics group
The ATLAS muon system will be equipped with high pressure drift tubes aiming for excellent position measurement of the muon tracks.Detailed simulations of the detector response to charged particle tracks made the study of all the pieces of information, contained in the wire chamber signal, possible. Front-end schematics as well as ideas how to encode several pieces of information into one output channel are presented.
Gyorgy Rubin, Peter Csato, Tivadar Kiss, Zoltan Meggyesi, Janos Sulyan, Laszlo Szendrei, Gyorgy Vesztergombi (RMKI, Budapest)
Gabor Harangozo, Jozsef Harangozo, Istvan Novak, Sandor Szilagyi (BME, Budapest)
Pierre Vande Vyvre (CERN, Geneva)
In this paper we present the development of the ALICE Detector Data Link (DDL) prototype which has been developed by RMKI, BME and CERN for the special needs of the ALICE experiment. This link provides high-speed transmission of data blocks (e. g. event data, thresholds, pedestals) in both directions between the front-en electronics and the data-acquisition system. The DDL can also be used as a transmission medium for the remote control and test of the front-end electronics during the normal operation and for the remote debugging during the system integration of the ALICE detector. A first prototype will be used in the ALICE-TPC test system.
J.M. Seixas, L.P. Caloba, A.S. Cerqueira
COPPE/EE/UFRJ, C.P. 68504, Rio de Janeiro 21945-970, Brazil e-mail:
seixas@lacc@ufrj.br Fax: 55-21-2906626 Tel: 55-21-2807393
CERN - PPE division. e-mail:seixasj@vxcern.cern.ch
An active adder for building the trigger tower signals required by the first-level trigger system for the scintillating tile calorimeter is described. It is designed to handle fast signals (50 ns width) that have to be linearly combined over a wide dynamic range (10 bits). Five differential signals coming from the three sampling layers of the calorimeter can be combined and the adder's output is also differential. Successful tests of the proposed circuit interfacing with shaper boards currently being used for testbeam purposes are also reported.
A. Kugel, J. Ludvig, R. Männer, K.-H. Noffz, S. Rühl,
M. Sessler, H. Simmler, H. Singpiel, R. Zoz
Universität Mannheim, Germany
J.R. Hubbard, P. Le Dû, M. Smizanska
Centre D'Etudes Nucleaires De Saclay, France
There are several different concepts for the ATLAS Level-2 trigger under investigation, all of which have to cope with the following challenges
These above problems could be resolved by a hybrid trigger combining an FPGA-processor and a processor-farm. The inserted FPGA-processor layer executes simple reconstruction algorithms and applies loose physics selection criteria. These criteria already reject ³ 80% of the events with a high - pt trigger and reduce the bandwith by a factor of 6 in regard to the full scan TRT. This would scale down the farm and strongly reduce the networking requirements.
The FPGA-processor layer and the farm together build a cost e ective hybrid solution for the level-2 trigger.
S. Dasu, M. Jaworski, J. Lackey, W. H. Smith
University of Wisconsin, Madison, WI, USA
The CMS level-1 trigger system carefully sifts the 40 MHz data to retain only interesting physics signals at 100 KHz level while discarding the well known QCD background. The level-1 calorimeter trigger electronics discussed here is designed to identify signatures for high energy electrons, photons, neutrinos and jets. The electron/photon trigger algorithm involves local isolation cuts requiring sharing of data amongst neighboring regions. The jet and neutrino trigger algorithms require additions of energies from large number of trigger towers. Both the algorithms are implemented in high-speed custom integrated circuits to satisfy the required short latency for trigger decision. We report about prototype construction and testing program which was instituted in order to demonstrate the crucial features of this trigger system. We fabricated prototype adder ASICs which sum eight 10-bit signed numbers in a total of 4 clock-steps at 160 MHz. These ASICs built by Vitesse in GaAs technology, chosen for its speed and ECL output capability, have been tested to work at 200 MHz, well above our specifications. At the heart of the trigger system is a custom "backplane" which provides point-to-point links for data sharing between the various cards at 160 MHz. In order to test the feasibility of operation at high frequency we built a complete prototype backplane with 1419 differential point-to-point links. The clock signals on the backplane show rise and fall times below 1 ns with reasonable signal levels even when measured at the farthest card slot. We will discuss the performance of this backplane, the test cards that are under being manufactured and the Adder ASIC.
S Sumorok
Event building for Run II on the CDF experiment at Fermilab is specified as upto 300 events/s into Level 3 with an average event size of about 150 kB. The event must be assembled from fragments originating from about a dozen readout sources, with fragment sizes in the range from 10 to 30 kB, implying that individual links must function with speeds of upto 10 MB/s. We report on preliminary studies conducted at CDF with an ATM based event builder test system. Such a system is a possible candidate for the CMS experiment at LHC.
L. Berger 1 , R. Nóbrega 2 , J.C. da
Silva 2 , J. Varela 2,3
1- Tecmic, Lisbon;
2- LIP, Lisbon; 3- CERN
We present the principles of a method for trigger data synchronization at LHC. Themethod makes use of the LHC bunch gap and allows a resynchronization of the data every LHC orbit (88 ms). It relies on the distribution by the TTC system of a signal synchronous with the first bunch in the orbit, and is implemented by a couple of circuits, Sync Tx/Rx, in each trigger link. We report on the test of the first prototype implementation.
The NA57 Collaboration
Presented by O. Villalobos Baillie
School of Physics and Astronomy
The University of Birmingham
The NA57 experiment at the CERN SPS uses a new trigger system in which certain features which will later be implemented in the ALICE experiment can be tested. In NA57, it is envisaged that physics measurements will be carried out in parallel with tests of a variety of ALICE prototypes. The triggering and readout of physics detectors will be performed allowing independent dead times for each sub-detector, so as to make effcient use of the beam time. Detector specific past- future protection and extensive monitoring and diagnostic features are provided. We describe the design features for this system, and present test results.
G.Feofilov, O.Stolyarov, F.Tsimbal, L.Vinogradov, F.Valiev
St.Petersburg, Russia, Institute for Physics of St.Petersburg State
University
V.Kasatkin, V.Kuts, O.Zhigunov, V.Platonov
St.Petersburg , Russia, Central Scientific c Research Institute
"Granit"
W.Klempt, A.Rudge
CERN, Geneva, Switzerland, European Organization for Nuclear Research
V.Lenti
Bari, Italy, Dipartamento di Fisica dell'Universita and Sezione INFN
O.Villalobos Baillie
Birmingham, United Kingdom, School of Physics and Astronomy
L.Efimov
JINR, Dubna, Russia, Joint Institute for Nuclear Research
We present design details and new measurements of the performance of fast electronics for the Forward Multiplicity Detector (FMD) for the ALICE experiment, based on Microchannel Plates (MCP). These detectors give the first trigger decision in the ALICE experiment. Fast passive summators are used on the detector for linear summation of up to eight isochronous signal channels from MCP pads. We present measurements of the performance of these summators, working in the frequency range up to 1 GHz. New low noise preamplifier , based on the Rudge transimpedance preamplifier , have been built to work with these summators. The new design shows a considerable improvement in performance with the usable frequency range extended up to 1 Ghz.
Torsten Wildschek, Alexander Kluge
The track finder receives trigger primitives from drift tubes in the barrel and from cathode strip chambers in the forward muon system. It assembles those trigger primitives to tracks, assigns transverse momentum, direction and quality to tracks and transmits these data to the global muon trigger. We present the track finder algorithm, hardware implementation and the status of the FPGA prototype.