E.Atkin, Yu.Volkov, I.Ilyushchenko, S.Kondratenko,
Yu.Mishin, P.Khlopkov
Moscow Engineering Physics Institute (MEPhI), Department of
Electronics
volkov@eldep.mephi.ru
V.Chernikov, V.Subbotin, S.Tsvetkov
State Research Institute of Pulse Technique
The structures of several PCB varieties for a preliminary processing of wire tracker signals is described. Each channel of such a structure contains a successive connection of a preamp, shaper and comparator, implemented with both semicustom and full-custom analog chips. The PCBs are designed as four-layer ones, assembled with SMD technology and all have the same dimensions of 110*30 mm. sq.
The results of their experimental testing and comparison by speed, dynamic range, power consumption are presented.
The given PCBs are intended for application with various wire detectors, having a standard range of detector capacitances 5...20 pF and that of signal currents 1...200 mA.
A. Arkhangelsky, E. Atkin, S. Kondratenko , Yu. Mishin , A.
Pleshko , Yu. Volkov
Department of Electronics, Moscow Engineering Physics Institute
Kashirskoe shosse 31, 115409 Moscow Russia
E-mail: atkin@eldep.mephi.ru
The structure of an application specific semicustom array (ASSA), designed proceeding from the necessity and convenience of accommodating several identical front-end channels of the «preamp - shaper - comparator - output stage» type has been described. The circuit solutions of separate channel units are not fixed and can be chosen with account of the requirements of a specific physical experiment.
A version of an ASSA implementation with the bipolar process of the research institute «Pulsar» (Moscow) (unity gain frequency of npn-transistors about 7 GHz) has been considered. The nearest planned application of ASSA is the manufacture of front-end ICs for use in the LHC experiments with wire trackers and time-of-flight systems of the plastic wall type.
P. Bailly, J. Chauveau, J.F. Genat, J.F. Huppert, H.
Lebbolo, L. Roos, Zhang Bo
LPNHE , Universite de Paris 6 et 7 , 75252 Paris Cedex, France
A 16-channel digital TDC chip has been designed in the context of the DIRC Detector for the BaBar experiment at the SLAC B-factory (Stanford, USA). Binning is 0.5 nanosecond, full-scale is 32 microseconds. A data driven scheme is implemented, since the chip integrates channel buffering and selective readout of data falling within a programmable time window. Use has been made of all design styles, analog full-custom for the TDC section and FIFO memories, and digital design synthesized from high level language hardware descriptions for the data processing functions. Tests have shown linearity performance better than 170 ps rms including binning noise. The chip is now under production.
C.Caligiore, D.Lo Presti, G.V.Russo
Physics Department, University of Catania and Sezione INFN, Catania
(ITALY)
A Cluster Finder for the ALICE ITS SDD Readout is proposed. It detects analog data cluster in the Analog Memory of the readout system. It consists of the Time Peak Detector (TPD) and the Centre Peak Detector (CPD). The TPD looks for the peak of the signal for each anode of the detector. A threshold remote control is provided to avoid the detection of gost tracks because of noise. The CPD, whose chip was already made in CMOS-1.2um technology, is mainly a Winner Take All. It compares the signals of three adjacent anodes when the central one has its maximum.
A.I.Chumakov, A.V.Yanenko, O.A.Kalashnikov
RAM single event upsets and total dose failures can be resulted from the LHC radiation environment. The approaches are presented to RAM radiation hardness for both error types evaluation and assurance. The radiation tolerant RAM units design principles and examples are discussed.
A.I.Chumakov, A.V.Yanenko, A.Y.Shevchenko
The simplified technique for predicting single event upsets from neutrons and protons in RAM is presented. It is based on Bendel approximation and Cf-252 tests.
The improvement of such approach is developed including tests for both different angle of particle beam incidence into sensitive volume and the particle energy attenuation. Additional alpha-particle isotopic tests for different supply voltage is proposed also.
The comparison between the prediction and experimental results is presented.
W. Fallot-Burghardt, W. Hofmann, K.T. Knoepfle, E. Sexauer,
U. Trunk
Max-Planck-Institut fuer Kernphysik
M. Cuje, M. Feuerstack-Raible, F. Eisele, B. Glass, U.
Straumann
Universitaet Heidelberg
HELIX128S-2 is the second version of a 128 channel readout chip designed for the silicon vertex and the inner tracking microstrip gas chamber detectors of HERA-B. It has been manufactured in the AMS 0.8um CMOS process.
A modified version (manufactured in the DMILL process) will meet the specifications for LHC-B vertex detector readout.
Measurements of the HELIX128S-2's performance are presented, as well as test results from new features.
Special emphasis will be given to the results of irradiation tests of the HELIX128-1 chip using a 137-Cs source.
Finally the radiation tolerance of the AMS CMOS processes in general will be discussed.
V.A.Telets, A.Y.Nikiforov and D.V.Gromov
The approach to smart sensor reliability, testability and radiation hardness regulation and assurance on the basis of microelectronics standards is presented. Smart sensor components are identified not only as measuring instruments but also as an original class of integrated circuits (IC) with the corresponding general-purpose parameter's system for basic applications. The conventional IC general specifications, radiation hardness requirements and qualification technique standards are suggested to be adopted and adjusted to this new class in particular supplements. Thus the Microelectronic and metrological terms and parameter systems within SCIC are analysed in details. The examples of the introduced outlook implementation positive experience in thermal, pressure, radiation and optical sensors design and tests are presented and analysed.
O.A.Kalashnikov
The approach to numeric simulation of digital units total dose functional failures is presented. It is based on the criterion membership functions method of the fuzzy logic sets theory. This approach allows to research the failures of digital LHC electronic units in various operation modes.
E. Atkin, Yu. Volkov, P. Khlopkov
Department of Electronics, Moscow Engineering Physics Institute
Kashirskoe shosse 31, 115409 Moscow Russia
E-mail: khlopkov@eldep.mephi.ru
On the basis of a previously elaborated ASIC, there has been designed and manufactured a discriminator PCB for precise timing signal generation. Particular attention is paid to the reproducibility of the characteristics, since the discriminators are intended for application in multichannel physical research equipment (hundreds and thousands of channels).
The expected timing accuracy is ±60 ps (FWHM) for input amplitudes of 30 mV to 2 V with a rise-time of 3 ns (in the CFD mode). This value is confirmed by the testing results of functional bread-board prototypes. The input signals thereat can be both positive and negative. The dimensions of a multilayer SMD PCB containing one discriminator channel are 40x100 mm. sq.
Tivadar Kiss, László Sáfrány,
István Novák, Bertalan Eged
Department of Microwave Telecommunications, TU of Budapest
As a part of the ALICE DDL project, experimental, 1.06 Gb/s media interface cards have been designed and tested. Two versions of the circuit have been realized with different PCB stack-up and power supply filtering methodes. In addition to the functional tests, thoroughful signal integrity measurements have been carried out. After evaluation of the measurements, the PCB design of the integrated DDL SIU and DIU cards can be optimized.
S. Szil·gyi, Z.Meggyesi, J.Harangoz
Technical University of Budapest (BME), Hungary
G.Rubin,
Research Institute for Particle and Nuclear Physics (RMKI), Budapest,
Hungary
The Data Acquisition systems in LHC experiments will require several thousands of high speed and reliable data links. Special, not yet standardized solutions in communication protocols such as ALICE-DDL necessitate modeling and simulation in the development phase. The use of a formal description technique leads to early design error detection and reduces the development cost. LOTOS is a formal description language which can provide formal support to a large part of the design cycle. The model can serve as a means with which we can study the structure of the protocol, and its completeness and logical consistency. The validation model defines the interactions of processes in the system, without resolving implementation details.
A.Y.Nikiforov, A.I.Chumakov, V.S.Figurov, P.K.Skorobogatov and V.A.Telets
Bulk CMOS IC operating in LHC environment are sensitive to latch-up effect due to electromagnetic and radiation influences. In this work the latch-up inspection and screening technique is developed and tested. The approach is based on the latch-up triggering by laser pulses - in this case latch-up parameters are in a good agreement with those in real LHC environment.
The latch-up 2D-numerical simulation together with experimental tests was performed on commercial and radiation hard bulk CMOS IC as well as on specialized test structures.
Latch-up general sensitivity and margins are obtained from CMOS IC laser tests within the power supply voltage and temperature range. The developed latch-up screening technique gave the possibility to detect and investigate latch-up windows effect in the high temperature range.
A.Y.Nikiforov, P.K.Skorobogatov, A.V.Artamonov, V.A.Telets,V.S.Figurov, S.A.Polevich
Multichip diode bridge assembly transient radiation effects are investigated. A good agreement is obtained between comparative laser and two-dimensional software simulations results of the single diode in spite of the essential metal shadowing. The diode bridge assembly transient response PSPICE simulation is found to be in good mutual correspondence with flash radiation test results.
A.Y.Nikiforov, V.A.Telets, A.I.Chumakov, P.K.Skorobogatov, A.I.Sheremetyev
In this paper the radiation hardness of small-scale production ASIC for LHC applications is analysed and the assurance concept is developed based on the simulation inspection and screening tests usage requirements.
The radiation hardness assurance procedure is developed including dominant radiation effects determination, process and structure inspection, particular ASIC design project qualification and chip hardness screening.
Specialized test units are designed in Bulk CMOS and CMOS/SOS processes and their simulation test results are obtained and analysed.
A.S.Artamonov, A.A.Demidov, O.A.Kalashnikov, A.Y.Nikiforov, S.A.Polevich, V.A.Telets
The approach, technique and equipment are presented aimed at ADC and DAC IC radiation hardness inspection and screening tests. They are based mainly on the simulator sources and universal testing tools usage and adopted to nuclear physics environment.
The typical Bulk CMOS as well as CMOS/SOS converters X-ray simulation tests have been carried out to demonstrate the developed technique and instruments efficiency. The measured conversion parameters degradation results are presented and analysed.
The designed technique and instruments can be recommended for ADC and DAC ICs radiation tests within LHC electronics design.
I.N. Alexandrov, N.M. Nikityuk
Joint Institute for Nuclear Research
E-mail: nikityuk@uct167.jinr.dubna.su
A short revew of the known coding schemes where superimposed codes are used is given. Peculiarity of these codes is that they can be used both for coding light signals and in hodoscopes (MPC, MSG, RPC and semiconductor detectors) where weak electrical signals are registered. It is important that light mixers (PMs) and electronic amplifier - mixsers can be used for parallel compression of data. Special characteristics of codes usefull for hodoscopes with light coding and methods for designing superimposed codes having optimal compression coeficient for multiplicity t = 1 with cluster, t = 2 and t > 2 are considered. The use of compressed data which can be decoded by means of PROMs leads to essential decrease of the number of data channels and accordingly, active elements. We show what way the superimposed codes can be used for fast event selection. Several coding matrices having such an optimal parameter as compression coeficients for multiplicity t > 2 are suggested. Iteration superimposed codes for large channel regstration n > 1000 and multiplicity > 2 are investigated and suggested. The suggested method for data compression can drastically change the approach to fast indetification cation of muon tracks on the ATLAS installation. The ALTERA technology is used for simulation of the schemesn, having 28 inputs and 8 outputs and the results of simulation are given.
C.PETTA - Dipartimento di Fisica dell'Universita' e Sezione
INFN, Catania, Italy
G.V.RUSSO - Dipartimento di Fisica dell'Universita' e Sezione INFN,
Catania, Italy
M.RUSSO - Istituto di Ingegneria El. e Tel. e Sezione INFN, Catania,
Italy
Two layers of the Inner Tracker System (ITS) in ALICE will be arranged with large-area Silicon Drift Detectors (SDDs). They allow single-track spatial measurements with precisions up to 15-20 microns in both coordinates and good energy resolutions. An innovative readout system has been proposed for ALICE, performing on-line SDDs' data pre-processing with Fuzzy Logic (FL) techniques. Here, we show the preliminary results of the overall detector/readout simulated response to the realistic SHAKER event. The required spatial precisions are maintained by the system, but the total amout of information carried on is reduced, in comparison with the traditional readouts and analysis.
N.RANDAZZO and G.V.RUSSO
Dipartimento di Fisica - Universita' di Catania and
INFN sezione di Catania
We present a first prototype of 16 channels transimpedece amplifier. This amplifier was designed taking in account the constrains from physics consideration in the two planes of Silicon Drift Detector (SDD) of the Inner Tracking System (ITS) in the ALICE detector, that must be used for future experiment at LHC. The amplifier was realized in 1.2um CMOS technology. Experimental measurements in accordance with theoretical predictions and simulations, show an ENC = 340 e- with transresistance of 150 Kohm and a bandwidth over 20 MHz with power consumption of 0.88 mW/channel.
G.Dumont. B.Righini
Direct cooling of VMEbus electronics modules, by addition of individual coolers, has been tested. Water cooling of the power supplies is in progress. Tests of these units in magnetic fields as expected for the ATLAS experiment are prepared.
M.Russo and G.V.Russo
Istituto di Informatica e Telecomunicazioni
Facolta' d'Ingegneria
Universita' di Catania (ITALY)
Fuzzy Logic (FL) is applied in several fields. Recently FL was applied in High Energy Physic Experiments (HEPEs). The first HEPE studies about FL were the design and implementations of Fuzzy Processors. The main drawback of these studies was the complete lack of knowledge about the requirements of a Fuzzy System (FS) in HEPE. So first FP were very speed, but too general purpose. In this paper we will describe GEFREX, the latest version of a Rule Generator (RG) able to extract in a supervised manner FSs. With GEFREX we are characterizing FSs in HEPE. So we are refining previous FP architectures to obtain the required speed in HEPEs. Further we are defining the necessary prerequisites of a learning accelerator card able to perform an on-line calibration.
P.K.Skorobogatov, A.Y.Nikiforov, I.V.Poljakov
CMOS SOS IC's elements two-dimensional numerical simulation is performed and the appropriate simplified analytical models are developed taking into account transient radiation effects. The simulation results demonstrated the dependence of the transistor ionising current and recovery time on the floating body potential. The numerical calculations are in a good correlation with experimental data obtained from the optical simulation tests.
P.K.Skorobogatov, A.Y.Nikiforov, V.M.Barbashov
Test method for IC electrical overstress (EOS) hardness estimation is introduced. It is based on test condition unification. The advantage of this method is a possibility of different IC's comparison from the point of hardness to electrical interferences during LHC experiments.
Specialized test system is developed for estimation of various IC's hardness to EOS including transient as well as permanent effects. The experimental data for CMOS RAM and bipolar linear preamplifier are presented.
Richard Sumner and George Blanar, LeCroy Corporation
The features and performance of a CMOS integrated circuit controller for high voltage systems are described. This IC provides all digital and low voltage analog functions including amplifiers, DACs and an ADC, for a complete switching power supply. As many as 256 devices can be connected to a host computer system with a simple serial cable which provides digital communication and low voltage power. This new CMOS controller allows high voltage to be generated where it is needed (in a tube base, for example), without sacrificing the features of a conventional rack-mounted system.
This new controller chip joins other available LeCroy integrated circuits in providing low cost, high performance, commercially supported components for use in research instruments designed and built by laboratories and university groups as well as in commercial products.
J. Ardelean, R. L. Chase, A. Hrisoho, S. Sen, K. Truong, G.
Wormser
Laboratoire de l'Accelerateur Lineaire, LAL Orsay, 91405 Orsay,
France
In the context of the DIRC detector for the BABAR experiment at the SLAC B-factory (Stanford, USA), an analog chip is designed to receive from a PMT, through 50 Ohm coaxial cable, signals rising in 3 ns , falling in 8 ns and to provide a digital output for timing purpose and a multiplexed analog output, proportional to the input for spectral measurements. There are 8 channels per chip with a common gain adjustment for the preamplifier and invidual control for the offset and threshold etting. The discriminator sensitivity is 2 mV. The dynamic range is from 2 mV to 100 mV. The equivalent noise at the input is 100 mV. The RMS time dispersion is less than 550 ps for 3 mV threshold. The shaping amplifier is of bipolar shape with 80 ns peaking time and 2.5 V mean output voltage. The crosstalk between channels is less than 2%.