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B. Bennetts
LogicVision
DFT (Design-For-Test) for electronic devices and systems has come a long way since its start in the 1960s, evolving from internal scan/ATPG through Boundary Scan and, now, Built-In Self Test. This presentation will re-visit the fundamentals of the three techniques, look briefly at what tools are available for BIST, and demonstrate current application through recent applications.
G. Chiaretti
Italtel
Silicon Optical Bench Technology is a Silica on Silicon based Technology able to hybridly integrate a variety of optical devices: passive components (splitters, WDM, filters...), active devices (laser, pin detectors), and both of them. After a review of this technology, its contributions to the CMS Tracker Optical Readout Link will be described. Mass production capability and the efforts needed to reach low cost link solutions will be discussed.
D. Gee
Hewlett Packard
This paper will show you how the business planning system works in Hewlett-Packard. It will introduce to you a ten step methodology for developing intermediate range plans as well as reviewing how to create and execute a breakthrough "Hoshin" plan. The importance of structured reviews and the overall integration of the various elements of the planning process will also be discussed.
George A. Riley
HyComp, Inc. Marlborough, MA, USA
As improved semiconductor device fabrication leads to ever faster, denser chips, interconnection has increasingly become the limitation to realizable chip performance. Entering this decade, semiconductor manufacturers routinely placed the chips of the nineties into the packages of the sixties. However, since then, many novel packages have been introduced, including more than a score of "chip-scale" packages. Beyond those packages, the growing commercial availability of several improved methods for flip chip interconnection now offers to the designer the possibility of the ultimate chip-scale package; the chip itself, the "packageless package."
This paper elucidates several commercially available flip chip interconnection methods and describes their relative advantages and disadvantages from the user's perspective. Results and examples presented are based on HyComp's five years of trials and errors in designing, manufacturing, and testing chip-based flip chip hybrids and MCMs.
P. Smith
Matra-Marconi
Steve Watts
Brunel University
CERN's RD48 or ROSE (R&d On Silicon for future Experiments) Collaboration is investigating the radiation tolerance of silicon containing various impurities - oxygen, carbon, germanium and tin. The collaboration is concentrating on the problems of bulk damage with a clear objective of providing practical advice to the LHC experiments. There is now strong experimental evidence that more tolerant detectors can be made. Epitaxial material is found to be typically a factor two harder. Significant effects due to processing have also been seen. There have been many important advances in our understanding of bulk damage effects in silicon. The use of lower resistivity material is also an important issue that the HEP community needs to debate.
P. S. Winokur
Sandia National Laboratories
This presentation examines the role of commercial, radiation-tolerant, and radiation-hardened technology in high-energy accelerator applications. After a brief review of the radiation environment at the Large Hadron Collider, details of the design and manufacture of radiation-hardened microelectronics are given. The issue of availability of radiation-hardened ICs is discussed in light of a declining supplier base. Challenges associated with the use of commercial-off-the-shelf (COTS) technology in radiation environments are reviewed, including variability, qualification, and cost. A discussion of future technology trends is then provided in which susceptibility to total-dose and single-event phenomena are evaluated as technology scale toward submicron dimensions. The presentation ends with a discussion of Sandia National Laboratories strategy to meet its future needs for radiation-hardened microelectronics in defense and space applications.
W. Dabrowski a,b , F. Anghinolfi a ,
D. Campbell c , W. Gannon c , A. Grillo
d , P. Jarron a , J. Kaplon a,f , N.
Kundu g , D. LaMarra e , G. Meddeler
h , S. Picchiottino a , R. Szczygiel f
a CERN, Geneva, Switzerland
b Faculty of Physics and Nuclear Techniques, University of Mining and
Metallurgy, Cracow, Poland
c Rutherford Appleton Laboratory, Didcot, England
d Santa Cruz Institute for Particle Physics, UCSC Santa Cruz, CA,
USA
e University of Geneva, Switzerland
f Institute of Nuclear Physics, Cracow, Poland
g University of Oxford, Oxford, England
h NIKHEF, Amsterdam, The Netherlands
The binary readout architecture has been implemented in a single 128-channel chip using the DMILL technology. A prototype SCT128B chip has been manufactured successfully. It comprises all core blocks of the binary readout architecture: front-end, binary pipeline, derandomizing buffer as well as an internal calibration circuitry and an internal DAC for the discriminator threshold control. The ABCD chip is a development of the SCT128B which includes data compression and readout circuitry as defined by the SCT readout protocol. Test results on performance and radiation hardness of the SCT128B chip as well as the ABCD design will be presented.
The binary readout architecture for the readout of silicon strip detectors in the ATLAS Silicon Tracker (SCT) has been developed using the DMILL technology. Due to demanding requirements on low noise, high speed and low power dissipation, a bipolar technology is preferred for the front-end while the storage and control logic must be implemented in a CMOS technology. The DMILL 0.8 um BiCMOS technology offers good radiation hardness performance for a wide variety of devices: MOSFETs, fast BJTs, JFETs and high value resistors with low stray capacitance. It is therefore suitable for mixed signal chip architectures and offers a unique possibility to integrate fast low noise analog circuits and digital functions in a single chip. A prototype SCT128B chip which comprises most of the key block of the binary readout architecture has been designed and manufactured successfully. The preamplifier-shaper circuit is followed by a discriminator providing only 1-bit yes/no information. The signals delivered from the discriminator outputs are latched in the input register in the edge sensing mode and clocked into the pipeline. The input register provides also a function of channel masking and can be loaded with a test pattern allowing for testing of the digital part. The binary pipeline is realized as a multiplexed FIFO circuit. The applied architecture of the pipeline results in two very valuable features: low power consumption and a very compact layout. Upon receiving a trigger signal the data are transferred from the pipeline to the second level buffer which is a dual-port static RAM array 128-bit wide by 9-word deep. It serves as a derandomizing buffer which removes the fluctuations from the L1 trigger distribution. The hit patterns corresponding to each L1 trigger signal are held in the buffer until it is read out. The memory is addressed by two pointers, a write pointer and a read pointer allowing for simultaneous writing and reading. For each readout strobe the oldest data from the readout buffer is shifted to the 128-bit parallel-to-serial output shift register. The SCT128B chip, in addition to the basic functional blocks mentioned above, comprises a calibration circuitry for internal generation of calibration pulses. The amplitude of calibration pulses is set by an 8-bit DAC and delay of calibration pulses relative to clock phase is controlled by a delay buffer of 5-bit resolution. The discrimination threshold is controlled by an 8-bit DAC.
Based on the SCT128B prototype we have designed the ABCD chip which, in addition to all core blocks being already implemented in the SCT128 design, includes also a complete back-end readout circuitry designed according to the SCT readout protocol. The back-end readout circuitry provides two basic functions: (a) on-chip data compression so that only addresses of hit channels are transferred off the detector, and (b) sending data over the token ring connecting 6 chips together. A redundancy scheme in the back-end readout logic is implemented which in the case of a single point failure allows for reconfiguration of the token ring and skipping the faulty chip. All back-end readout blocks are functionally identical to those implemented in the ABC chip which has been designed for another technological option considered in the SCT. The first tests of the SCT128B chip show full functionality at a clock frequency of 40 MHz and basic parameters as expected. The design and performance of the SCT128B chip as well as radiation test results will be presented. Novel features implemented in the ABCD design will be discussed.
V. Arbet-Engels*, G. Cervelli, K. Gill, R. Grabit, C.
Mommaert, G. Stefanini, F. Vasey
CERN, CH-1211, Geneva 23, Switzerland.
* corresponding author, e-mail: vincent.arbet.engels@cern.ch
tel: +41 22 767 8583
fax: +41 22 767 2800
Optical links for the CMS experiment are being developed for signal transfer from the front-end electronics of the tracker. The static and dynamic evaluation of one-way prototype analogue links has been performed. These links are based on representative optoelectronic components (edge-emitting lasers and pin-photodiodes) to be used in the future readout system. Characteristics of both transmitters and receivers and the full link transfer function are presented. The overall performance is discussed in terms of static and dynamic responses. Preliminary results on digital links are also discussed.
The immunity against electromagnetic interference and low mass of lightwave communication technologies make optical links the method of choice for data transfer in the CMS experiment [1]. The optical link of the CMS tracker readout system is a 100m long uni-directional link consisting of directly modulated edge-emitting lasers [2]. Analogue data from 256 channels are multiplexed onto each fibre link and serially transferred at a frequency of 40 MS/s. The modulated signals are detected by photodiodes and digitised at the Frond End Driver (FED) board in the counting room. The demanding environment of the CMS detector (high irradiation levels, physical complexity, low power dissipation, and volume constraints) sets new technological challenges and requires a thorough analysis of the different building blocks of such an optical link.
In this work, we describe a prototype one-way optical link based on components representative of the target system. Transmitters consist of Fabry-Perot InGaAsP MQW edge-emitting lasers (( = 1.3um) driven by transconductance amplifiers (Gs Å 5.4 mS). Receivers are based on InGaAs pin-photodiodes DC coupled to transimpedance amplifiers. The responsivity of the photodiode is about 0.9 A/W and the amplifier gain is Å 10 k½. The prototype driver and receiver amplifiers are built using commercial ICs. Since the transmitters are located inside the detector volume, the radiation hardness of the optoelectronic devices, fibres, and connectors has been assessed [3].
Lasers, laser drivers, photodiodes, and photodiode amplifiers are individually characterized prior to the full link evaluation. The full links are then tested on evaluation platforms with independent receiver and transmitter circuit boards. The high modularity of these platforms permits testing of analogue as well as digital links. Their distribution to the experimental physics groups is under way.
A static measurement of the analogue link transfer characteristic is shown in figure 1. The input voltage range is ±300 mV beyond which the photodiode amplifiers start to saturate. The linearity, defined as the relative deviation from the measured averaged gain value, is also shown in figure 1. Linearity deviation of less than 2% is within the optical link target specifications . The equivalent input noise with the present link configuration is in the order of a few millivolts.
The dynamic performance of the analogue link was measured using a spectrum analyzer and figure 2 shows the optical link transfer function. The -3dB loss is at about 140MHz; this cut-off frequency closely corresponds to the bandwidth of the receiver transimpedance amplifier. Another figure of merit is the settling time within the 25ns sampling time period. For pulsed input signals with 1.4ns rise time, a 15ns settling time (to within 1% of the input signal) is reported.
In summary, a one way analogue optical link for the CMS tracker readout system has been fully characterized. The frequency bandwidth is in excess of 130 MHz and the deviation from linearity is less than 2%. The technology is extended to digital signal transmission with the demonstration a prototype fast digital link.
[1] The Compact Muon Solenoid Technical Proposal. CERN Report LHCC
94-38 (1994).
[2] G. Hall, G. Stefanini and F. Vasey, CERN CMS Note 1996/012.
[3] K. Gill and al., see presentation at this meeting.
Authors: R. Baur, P. Ernst, G. Gramegna , M. Richter
Universitaet Heidelberg, Physikalisches Institut, Germany
We present the development of new front-end electronics suitable for a Time Projection Chamber (TPC). The front-end chain is comprised of two circuits: (i) A charge sensitive amplifier (CSA) with semi-Gaussian shaper and tail-cancellation. The CSA is matched to a 12pF pad capacitance. We measure an equivalent noise charge ENC of 230 e rms at Ts=650ns. The peaking time can be selected between 180ns-650ns. The tail suppression can be externally tuned to cancel tails between 0.1µs-1µs. (ii) A 16x256 cell switched capacitor array stores the input waveform at 14 MHz during the drift-time of the chamber. A 16 channel successive approximation ADC sequentially digitizes the signal at 1 MHz with 8-bit precision. Although the circuits are geared towards the CERES/NA45 TPC, the necessary flexibility to accomodate different operating conditions make it feasible for the ALICE experiment.
Among the different technologies, the CMOS one offers the advantage of being inexpensive and readily available for full custom design [1]. Recently a CMOS Preamp-Shaper with tail cancellation has been developed for the STAR experiment at RHIC [2]. This circuit is based on a charge sensitive amplifier (CSA) with pulsed reset [3]. The drawbacks of the pulsed reset scheme are: (i) dead time, (ii) the system is blind until the next reset cycle if a large undesired signal is collected, (iii) digital signals are running on an analog low noise circuit. To address these issues we developed a general-purpose CMOS charge sensitive amplifier (CSA) and a CSA-Shaper with tail suppression to process the signal produced by an ionizing track across a Time Projection Chamber (TPC). Although the circuit is geared towards the CERES-TPC [4], its flexibility (needed to accomodate different operating conditions) makes it feasibile to use for the ALICE experiment as well [5]. The CSA-Shaper features a selectable peaking time in the range 200ns--450ns and can suppress tails with time constants between 0.1us-1us. We use a feedback resistance RF in parallel to CF to establishes the DC path: the charge signal integrated onto CF is continuously discharged with a decay time Tdecay=RF*CF. The value of RF is a trade-off between noise performance and capability to process events with high occupancy [6, 7]. For a peaking time Ts=400ns, noise considerations dictate a feedback resistance RF > 4MOhm. The only practical way to realize such a high resistance in CMOS technology is by using the associated drain-source resistance Rds(MF) of a MOSFET transistor. Rds(MF) depends on the biasing condition of MF, in particular decreases at Vgs(MF) increasing. Considering that Vgs(MF)=Vpreamp-Vg(MF), the integration of small charges results in small Vgs(MF) swings, thus Rds(MF) = Rds,DC(MF), its value being high enough not to worsen the noise performance. Conversely, large charges are discharged with a faster decay time and the CSA-Shaper's baseline is quickly restored. What is more important, undesired large signals (as delta electrons) collected on the TPC pad are transferred onto CF and quickly discharged minimizing the dead time. In order to use a MOSFET transistor as feedback resistance, two issues must be addressed: (i) how to prevent the gain linearity from being worsened by a non-linear resistance in the feedback loop. The voltage-charge conversion gain, which in an ideal CSA is 1/CF, is reduced if the ratio Tdecay/Trise is not high enough. In this condition, a variation of Tdecay affects the gain, and the dependence of Rds(MF) on the input charge worsens the gain linearity. (ii) How to bias MF in the MOhm region while tracking process, temperature, supply voltage variations (in particular the threshold voltage can change by +-100mV from chip-to- chip). The two issues have been addressed by using general purpose circuit techniques developed for continuously sensitive CMOS Preamp-Shapers. Two different CSAs, matched to 12pF and 20pF pad capacitance have been designed and fabricated with the 0.8um AMS CMOS process. We submitted also two alternative schemes to suppress the tail of the charge pulse.
MF is biased in the triode region by using a Self-Adaptive Bias technique proposed and implemented in a CSA for a Silicon Drift Detector to be used for particle tracking [8, 9] and in a CSA-Shaper for X-Ray Spectroscopy [10, 11]. In our case we introduced a feedback transistor MF with W/L=2um/40um to achieve 120 MOhm and 10 MOhm resistance for respectively the 12pF and the 20pF version. The Self Bias circuit makes Rds(MF) independent on process, temperature and supply voltage variations, and no external adjustement is needed to operate the circuit. The non-linearity of the CSA's gain (within 5% up to Qin=500fC, and within 2% up to 350fC) is a second order effect due to the dependence of Rds(MF) on Qin. The absolute value of the gain (G=1.16 mV/fC) is known within 20%, its calibration is now in progress. Since Rds(MF) depends on Qin, the use of a conventional Pole-Zero would worsen the linearity of the Preamp-Shaper's gain [12]. To solve this issue, we used an adaptive Pole- Zero cancellation scheme [8, 9, 11]. A MOSFET transistor Mzero and a capacitance Czero introduce a Zero to cancel the CSA Pole. Besides, Mzero is biased as MF during the dynamic swing, thus the Zero associated to the network Mzero-Czero, adapts itself dynamically to cancel the CSA Pole. In other words the second order effects of Rds(MF) on the CSA's gain is accurately suppressed in the CSA-Shaper. We have implemented two different circuits based on the classical tail cancellation scheme. One is a variation of the scheme implemented in [2], while the other scheme uses a third stage to introduce a Pole-Zero: the Pole provides additional shaping and the Zero can be adjusted to accurately cancel the tail of the charge signal.
The CSAs have been connected to an external shaper with selectable shaping time and the equivalent noise charge (ENC) vs. peaking time Ts has been measured. The CSA matched to 12pF has been measured in two bias conditions for MF, the self-biased and the pinched one (with Rds(MF)=2.5GOhm) achieved by forcing a proper voltage on the gate of MF. With MF pinched there is no parallel noise contribution and we measure ENC=120 e rms at Ts=27us for the 12pF version. In the self-biased condition at 700ns peaking time the ENC is 230 e rms and 300 e rms for respectively the 12pF and 20pF version. The uncertainty on the absolute value of the gain makes this noise performance accurate within 20%.
A new CMOS Preamp-Shaper with tail suppression which implements novel circuit techniques has been designed and fabricated with the AMS 0.8um process. The circuit is optimized the CERES-TPC, but necessary flexibility to accommodate different operating conditions make it usable for the ALICE experiment. The Preamp-Shaper with tail suppression features a selectable peaking time in the range 200ns-450ns and can suppress tails with time constants between 0.1um-1um. The scheme uses a MOSFET transistor MF to discharge continuously the charge signal integrated onto CF. Novel circuit techniques have been implemented to cope with the biasing of MF and its non-linear resistance. The advantages of the chosen scheme are: (i) no dead-time, (ii) no digital signals running on a low noise analog chip, (iii) no external components or adjustments needed to operate the Preamp-Shaper, (iv) fast baseline restoring in presence of highly ionizing tracks. The Gain of the CSA is equal to 1.16mV/fC. We plan to increase the gain by a factor four and reduce Rds,DC(MF) to 20MOhm in the final version. The noise performance of the CSA is 120 e rms at Ts=27us if MF is pinched and 230 e rms at Ts=700ns in the self-biased condition. The noise performance and the Gain are accurate within 20%, the gain calibration is in progress. Two different schemes for the tail suppression have been implemented and first tests have been started.
[1] Z.Y. Chang, W. Sansen, "Low Noise Wide-Band Amplifiers in
Bipolar and CMOS Technologies", Kluwer Academic Publishers, 1991, Ch.
5
[2] S.Klein et. al., Proceedings of the First Workshop on Electronics
for LHC experiments, CERN/LHCC/95-96, p.93.
[3] D.A. Landis, C.P. Cork, N.W. Madden, F.S. Goulding, IEEE Trans.
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[4] P.Holl et. al., CERES/NA45-Collaboration, Addendum to Proposal
SPSLC/P280, CERN/SPSLC 96-35, 1996.
[5] ALICE Technical Proposal, CERN/LHCC/95-71, December 1995.
[6] E. Gatti, P. Manfredi, Nuovo Cimento 9 (1986).
[7] V. Radeka, "Low-Noise Techniques in Detectors", Ann. Rev. Nucl.
Part. Sci. 1988, 38 , 217-77.
[8] G. Gramegna, P. O'Connor, P. Rehak, S. Hart, Nucl. Instrum. and
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(1982), 365-374.
G Bohner, Jean Pierre Mendiburu
In this paper, I describe the method foreseen to process the electronic calibration of the crystal Electromagnetic Calorimeter of CMS. The analog and logic circuits being developped at LAPP for this purpose are described.
Vincent BONZOM, Laurent BLANQUART, Pierre DELPIERRE
CPPM/IN2P3, 163 Av de Luminy, CASE 907, 13288 Marseille Cedex 9,
FRANCE.
Peter FISCHER, Stephan MEUSER, Norbert WERMES
PHYSIKALISCHES INSTITUT, Nussallee 12, 53115 BONN, GERMANY.
Several pixel readout chips for the ATLAS experiment at LHC have been designed and tested. The chip architectures are described and measurements of the chip performance are presented.
The LEPTON Chip is a matrix of 12*63 pixels with a complete End Of Column decoder which has been designed by the CPPM group in DMILL radhard technology. It has been sucessfully operated after an irradiation of up to 30Mrad.
The Beer-and-Pastis Chip is a matrix of 12*63 pixels. It includes a tune threshold system in each pixel and delivers the Time Over Threshold information for analog purpose. It has been designed in AMS BiCMOS 0.8u in collaboration with the Bonn Physics Institute. These two chips have been bonded to detectors and successfuly tested in beam.
A front end demonstrator chip is under design (FE-A, common work BONN-CPPM). It includes 18 columns of 160 pixels and a complete control and readout circuitry. It will be used in the ATLAS module which uses 16 chips on one silicon sensor substrate.
J. Beringer, K. Borer, R.K. Mommsen
Laboratory for High Energy Physics, University of Bern, Switzerland
E. Monnier
Centre de Physique des Particules de Marseille, CPPM
IN2P3 et Universite d'Aix Marseille II, Marseille, France
R.B. Nickerson, A.R. Weidberg
Department of Nuclear Physics, Oxford University, UK
H.Q. Hou, K.L. Lear
Sandia National Laboratories, Albuquerque NM, USA
We present the final results of radiation hardness and life time studies of Light Emitting Diodes (LEDs) and Vertical Cavity Surface Emitting Laser diodes (VCSELs). About 250 LEDs from two different manufacturers and about 200 VCSELs produced by Sandia National Laboratories have been exposed to neutron and proton fluencies up to twice those expected at the inner tracker of ATLAS. We report on the radiation damage and the required conditions for its (partial) annealing, and we present post-irradiation failure rates of LEDs and VCSELs during several months of operation at increased temperature.
Summary prepared by M. Campbell, E. Cantatore, E.H.M.
Heijne and W.Snoeys
representing the RD19, WA97 and NA57 collaborations
ECP Division, CERN, Geneva, Switzerland
The development of a large area detector pixel system requires a significant effort beyond the single readout cell design. We will describe some of the problems we experienced and the solutions we applied to obtain a working and reliable pixel system for the WA97 experiment. These cover the assembly of the cells into a full readout chip, of readout chips and detector into a detector unit, and of different detector units onto a substrate to cover a large area. The development carried over several generations of readout chips. We feel the experience gained is essential in the development of working and reliable detector systems for LHC.
In a hybrid pixel detector the readout chip containing a two-dimensional matrix of low-noise readout cells is mated to the detector chip by solder bumps. For the omega3/LHC1, the latest generation of readout chips [1], one more metal layer allowed extra shielding. Experimental comparison with the previous generation (omega2) [2] confirms that this shielding was quite effective in preventing coupling of signals on the electronics chip into the detector chip.
We demonstrate that feasibility of multi-chip arrays depends crucially on the availability of tested, fully functional components (Known Good Die) and one has to study the yield and reliability at all levels in the assembly in order to obtain in the end satisfactory arrays. While the probability to be fully functional after testing was about 90 % only for the omega2, full testability has been achieved for the omega3/LHC1.
This full testability also allowed to gather a wealth of information with regard to chip uniformity and chip-to-chip uniformity of pixel cell performance, also crucial in practical detector systems. As an example among many, figure 1a. shows a systematic top-down variation in the threshold distribution along the matrix, obtained after the first measurements on the newly arrived omega3/LHC1 chip. The cause of this effect was a tiny (~10mV) resistive drop along the Vdd line connected to the front-end. This was fixed in a later submission of the LHC1 as can be seen in Figure 1b.
The next step to build a large pixel detector consists in assembling the detectors and the readout electronics on a suitable carrier. A multi-layer ceramic was produced for the mounting of the LHC1 chips in the NA57 telescope (Figure 2). The substrate is a thin ceramic (300um) on which two metal planes (Vdd and Vss) and 3 signal layers are deposited, separated by 30um of ceramic dielectric.
The availability of full metal planes for power distribution avoids chip performance degradation due to resistive losses and ensures a good supply stability even for large current changes. This is a great improvement over the omega2 single layer ceramic substrate with no full planes for power distribution, where one needed to wait many microseconds after a reset before being able to detect a new event. Resistive losses should not affect analog bias currents and references to the chips either. By adjusting the bias current controlling the internal delay for every chip individually [3], the width of the overall delay distribution on a 24 chip array could be limited to only 2 times the width of the single-chip distribution.
In the last WA97 (omega) run at CERN, a pixel detector telescope containing 7 planes of 5 by 5 cm was successfully operated : it contains 5 omega2 and 2 omega3/LHC1 planes or about 700000 pixel channels. Several planes based on the improved version of omega3/LHC1 with its better threshold uniformity are currently under construction for the NA57 experiment.
The implementation and the use of a pixel detector on a somewhat larger scale has allowed us to gain valuable experience in the development of pixel systems for LHC. Several issues still have to be addressed further : the requirement of very low mass pushes towards the integration of the busses on the silicon detector using silicon substrate MCM technology [4], increasingly fast signals need to be transferred over the lines, several experiments require radiation tolerance to a more or less severe extent, and performance under irradiation needs to evaluated and improved further not only on the chip level, but also for the full system.
[1] E. H. M. Heijne et al. LHC1: a Semiconductor Pixel Detector
Readout Chip with Internal, Tunable Delay, Providing a Binary Pattern
of Selected Events Nuclear Instruments and Methods in Physics
Research A 383 (1996) 55-63
[2] E. H. M. Heijne et al. First operation of a 72k element hybrid
silicon micropattern detector array Nuclear Instruments and Methods
in Physics Research A 349 (1994) 138
[3] E. Cantatore et al. Statistical Analysis and Optimisation of
Delay Line Chains for Pixel Readout Electronics Presented to the 3rd
Int. Workshop on Semiconductor Pixel detectors for Particles and
X-rays March 24-27, 1996, Bari, Italy To be published by Nuclear
Instruments and Methods in Physics Research
[4] K.H. Becks et al. A multichip module, the basic building block
for large area pixel detectors Proceeding of the 1996 IEEE MCM
Conference Monterey, CA, USA, January 1996
G.Cervelli*, C.Mommaert, V.Arbet-Engels, K.Gill, R.Grabit,
G.Stefanini, F.Vasey
CERN, CH 1211 Geneva 23, SWITZERLAND
The CMS tracker readout will make use of analogue optical links. In order to simulate and characterise their functionality within a complete readout chain, a software program has been developed in a LabVIEW environment. It allows for interchangeability of software modules and real hardware components in a transparent and modular way, so that both full software and mixed hardware/software simulation of the chain are possible. We present the characterisation of a full readout chain and a study of the readout chain specifications, based on Monte Carlo simulation techniques and statistical analysis of system parameters.
The CMS tracker readout chain will make use of optical links to transmit pre-processed analogue information from the front-end chips (APVs) to the front-end drivers (FEDs) [1]. This chain is partitioned into blocks (APV, optical link, FED), which are developed and evaluated by different groups working in parallel. To evaluate single blocks in a realistic environment the simulation of the rest of the chain is required. We have chosen a software oriented approach to investigate the optical link functionality within a complete readout chain. Each element of the chain is either simulated or addressed via A/D and D/A converters. The program is modular and uniform: both mixed software/hardware and full software simulations are performed in a LabVIEW environment. Typical applications range from simple characterisation, to system level simulation, algorithm prototyping, and investigation of alternative concepts.
The concept of the simulation is depicted in Fig. 1. Stimulus signals are generated in vectorial form and are passed to the system under test, i.e. the readout chain (APV, optical link, FED).The hardware of the optical link and the FED have been installed in the lab. The APV chip is only simulated. If real signals are required to feed the hardware chain components, they are downloaded to an arbitrary function generator (D/A conversion). The response of the system is read in digital form through an A/D converter (oscilloscope or VME board). The system evaluation module executes a specific characterisation of the system depending on the injected stimulus (calibration signals and/or real events). This includes static evaluation (gain and non-linearity), dynamic evaluation (response times and transfer function), and noise evaluation. The validity of the software models is verified based on measurements of both individual link components [2] and overall chain. As an example, the simulated and measured optical link transfer functions are compared in Fig. 2. Statistical analysis of the system parameters is executed at a further stage. Repeated calls are made to the system evaluation module, either over time or for different system channels. This allows the study of the correlation with time varying environmental parameters (radiation dose, B-field, etc.), or the statistical evaluation of the parameter spread between different channels.
A major advantage of our software tool is its modularity (easy 'plug-in' of real and/or simulated components). The evaluation criteria (i.e. dynamic range, linearity deviation, etc.) are general and independent of the particular system-under-test structure, and could therefore be of interest to many other groups. Using the mixed hardware/software option, we will present the emulation of the APV chip (play-back of real data through the APV simulator, including dynamic behaviour and stochastic L1 triggering), the evaluation of the real (not simulated) optical link, with both calibration signals and real events, and the evaluation of a complete readout chain, from APV to FED, including the real optical link and the real FED. In addition, the purely mathematical description of the system, based on a Monte Carlo technique, allows us to simulate the statistical combination of the parameter tolerances over a large number of channels, and thus represents an efficient method to study and define system specifications.
[1] G. Hall, G. Stefanini and F.Vasey, CERN CMS Note 1996/012.
[2] V. Arbet-Engels et al., see presentation at this meeting.
Corresponding author: Giovanni Darbo
INFN
Via Dodecaneso 33
I-16146 Genova Italy
eMail: darbo@genova.infn.it
Fax: +3910-353 6319
Tel.: +3910-353 6454
The System Architecture of the ATLAS pixel detector will be organized around 3 kind of chips: a front-end (FE) chip, a module controller chip (MCC) and a ladder controller chip (LCC). The FE chip has 3840 analog front-ends directly bump-bonded to the detector matrix and a back-end logic that does data sparsification and event time stamp. The MCC does event building, error handling and it has trigger and timing control logic. The LCC is the last chip in the chain and its function is the routing of event and control data from several MCC's to the off-detector electronics.
In the talk we describe the system architecture and we report on the its impact to the physic events. Some results from prototype chips will be also illustrated.
F. Corsi*, D. De Venuto+, V. Lenti^
* Department of Electrical and Electronics Engineering Polytechnic of
Bari, via Orabona, 4 70125 Bari, Italy, E-mail:
corsi@vaxba0.ba.infn.it
+ Faculty of Engineering, University of Lecce, via per Monteroni,
73100 Lecce, Italy E-mail: daniela@deeetr02.poliba.it
^ INFN and University of Bari, Italy
A new method to test the dynamic performances of analogue and mixed-signal integrated circuits is proposed, which is based on fault signature generation starting from the state space analysis of linear circuits.
By sampling the response of the circuit under test (CUT) to a simple rectangular pulse, a set of parameters alphas, functions of the circuit singularities, is evaluated, which constitute a signature for the CUT. Amplitudes perturbations of these parameters engendered by element drift failure, constitute a fault signature. The proposed testing procedure has been successfully applied to a typical analogue front end for direct readout of pixel detectors, which is generally constituted by a charge sensitive amplifier and shaper used in LHC experiments.
Its common knowledge that testing analogue circuits is a difficult problem. The complexity of the analogue circuits testing compares unfavourably with that of digital circuits. In particular, we have in analogue circuits complex functions, performances and specifications defined in a continuum while the digital circuits realize structured functions (truth table and state tables). The analogue circuits are affected by high noise sensitivity, while the digital ones are relatively immune to noise. Moreover, the absence of well defined fault models in the analogue circuits makes, in most cases, the specification driven testing more attractive than the fault driven one used for digital circuits. Under this hypothesis, an analogue circuit can be considered faulty if at least one of the defined specifications is not fulfilled. So, in principle, all the performances should be checked in order to accept a circuit under test as good. This kind of approach is usually time consuming.
A remarkable speed up of the testing procedure is made possible by identifying a subset of circuit specifications which cover the whole set, as described in [1-2], and then by ordering this subset to maximize the probability of detecting a faulty circuit as soon as possible.
An alternative solution consists in assuming a suitable performance of the circuit as its signature: the circuit will be accepted or rejected on the basis of its signature and the decision made will be affected by a certain degree of statistical confidence.
The method proposed here [2-3], is based on the properties of a set parameters, alphas, measured by sampling the circuit response to a rectangular pulse. To achieve optimal sensitivity, the width of the rectangular pulse has to be determined on the basis of the pole locations so as to cover the nominal circuit bandwidth. Starting from the specifications defined on the circuit performances, it is possible to identify an acceptability domain for these parameters. The test is then simply accomplished by checking that the actual circuit parameters belong to the acceptability region. The testing strategy has been successfully used on both classical OPAMP based active filters and mixed-signal filtering systems [4-8].
Here it is described the application of this testing methodology to a front-end circuit for pixel detectors like those used in LHC experiments. The circuit is composed by a charge sensitive preamplifier (CSA) and a pulse shaper. The amplifier consists of a cascode gain stage followed by a unity-gain level-shifting source follower.
In order to test the CSA, the exact time response for an input current pulse has been evaluated by SPECTRE simulation. The CSA transfer function in the frequency domain is generally a second-order one, then only two alphas parameters are needed for its test. In particular, one of the two poles is equal to the unity loop gain frequency (GWB) of the charge feedback loop. Therefore, its position is very important in studying the stability of the CSA. The time domain response Vout(t) is an exponentially rising step with a slowly decaying tail governed by the dc feedback resistance depending from the two time constants t1 and t2 , where, in all practical cases, t2<< t1.
The rise time of the step signal tr is defined as 2.2*t2 or 2.2Ct/(Cf*GWB*2pi). So, for a given detector capacitance, the rise time can be minimized by increasing the GBW of the preamplifier and using a large feedback capacitance. Since the feedback capacitance is normally set by the sensitivity or gain requirement of the CSA, a fast response requires a large GBW. The fall time is determined by the time constant t1 and mainly by the feedback resistance Rf as Cf is normally fixed by the gain requirement.
The degradation of the CSA parameters (parametric faults) affects both the poles and the alphas. In this way, by sampling the pulse response of the CSA and evaluating the new alphas positions, it is possible to control all the dynamic specifications which are connected with the pole positions (GBW, cut-off frequency, peaking time, etc..) and most of the static ones connected to individual resistance values.
At the same time it is possible to test the shaper since all its specifications are connected to the poles and then to the alphas.
A supply current (IDD and ISS) testing strategy, based on the application of a built-in-current (BIC) sensor can be used to provide additional coverage for those faults more directly connected to the active devices employed in the CSA and in the shaper.
Table : Results of the front-end test for parametric faults
|
T=10.5ns |
Good circuit |
Fault #1 |
Fault #2 |
Fault #3 |
Fault #4 |
|
alphas1 |
-1.3298 |
-1.258 |
-0.855 |
-0.216 |
-0.737 |
|
alpha2 |
0.3874 |
0.351 |
0.144 |
0.178 |
-0.065 |
Faulty condition #2 : CSA feedback capacitance decrease of 50%.
Faulty condition #3 : CSA feedback capacitance increase of 50%.
Faulty condition #4 : Shaper feedback capacitance variation.
1. Ruey-wen Liu, 1991, Van Nostrand Reinhold, New York.
2. L. Milor, A. L. Sangiovanni-Vincentelli, 1994, IEEE Tran. on CAD
in Integrated Circuits and Syst., no. 13.
3. H. H. Schreiber, 1979, IEEE Tran. on Circuits and Syst. 7,
CAS-26.
4. F. Corsi, D. De Venuto, C. Marzocca, et al., 1995, in Proc. of 2nd
Advanced Training Course: Mixed Design of VLSI Circuits, Krakow,
Poland.
5. D. De Venuto, E. Cantatore, G. Gramegna, C. Marzocca, F. Corsi,
1996, in Proc. of MELECON,96 Bari, Italy.
6. D. De Venuto, E. Cantatore, F. Corsi, 1996, in Proc. of European
Test Workshop; Sete, Montpellier, France.
7. E. Cantatore, F. Corsi, D. De Venuto, C. Marzocca, et al., 1996,
in Proc. of DCIS'96, Barcelona, Spain.
8. F. Corsi, D. De Venuto, C. Marzocca, 1997, in Proc. of European
Test Workshop; Cagliari, Italy.
M. Dentan, P. Abbon, P. Borgeaud, E. Delagnes, N. Fourches,
D. Lachartre, F. Lugiez, B. Paul, M. Rouger;
CEA-DSM-DAPNIA Saclay, F-91191 Gif-sur-Yvette, France.
R. Truche, J.P. Blanc, O. Faynot, C. Leroux, E. Delevoye-Orsier,
JL. Pelloie, J. de Pontcharra;
CEA - Technologies Avancées - LETI, F-38054 Grenible Cedex 09,
France.
O. Flament, JM. Guebhard, JL. Leray, J. Montaron, O. Musseau, A.
Vitez;
CEA - Centre d'Etudes de Bruyères-le-Châtel, F-91680
Bruyères-le-Châtel, France.
L. Blanquart(1), V. Bonzom(1), P. Delpierre(1), R. Potheau(1), A.
Hrisoho(2);
IN2P3: (1) CPPM, F-13288 Marseille, France; (2) LAL, F-91405 Orsay
Cedex, France.
DMILL is a mixed analog-digital rad-hard (> 10 Mrads, > 1014 n/cm2) technology, which integrates, on an SOI substrate, 0.8 um CMOS, a vertical npn bipolar transistor and a P-type JFET. DMILL was developped by the CEA between 1990 and 1995. Its transfert to the industrial production line of TEMIC / Matra-MHS at Nantes (Fr.) started the end of 1995 and is now complete. This technology, which possesses exceptional features, is available for fabrication of prototypes, since April 1997 in the framework of MPCs organized by Europractice. DMILL will be available for mass production from October 1997.
Technological choices
DMILL uses an SOI substrate which significantly reduces the sensitivity of the circuits to transient effects such as parasitic currents or memory cell upsets, induced by passage of an ionizing particle.
The DMILL CMOS transistors are separated by a dielectric trench which definitively eliminates any possibility of latch-up (i.e. locking of a thyristor structure consisting of two juxtaposed complementary MOS transistors. Latch-up, initiated in standard technologies by the passage of an ionizing particle, results in circuit malfunctions and, in some cases, in their definitive destruction).
The 0.8-um CMOS and the vertical bipolar transistor of DMILL provide the advantages of present BiCMOS technologies. The JFET transistor is used for a number of low-noise or low-temperature applications.
The CMOS structure was designed to obtain high hardness to ionizing radiation and a low noise level. This type of transistor, which use majority carriers, is naturally hardened to neutron-type radiation.
The bipolar transistor uses a vertical structure which provides both high neutron-hardness and high speed operation. Its structure was optimized to obtain high hardness to ionizing radiation.
The JFET transistor, which use majority carriers and whose intrinsic operation does not involve oxides, naturally has low sensitivity to ionizing radiations and neutrons. Its structure was optimized to obtain very high hardness to these radiations types.
For analog applications, DMILL integrates two capacitor and two resistance families, both radiation hardened.
DMILL also integrates hardened anti-ESD devices, specially designed for protection of either analog or digital circuits.
The interconnections can be made with two metal layers whose minimum dimensions are those of a 0.6-um technology, and with a polysilicon layer.
The design rules for the components and their interconnections were specifically optimized to obtain a high integration density, which is comparable to that of present 0.6-um CMOS technologies.
Industrial transfer
The stabilization of the DMILL process was completed at the beginning of 1995 at LETI (Grenoble, France), which is the microelectronics development laboratory of the CEA. In September 1995, TEMIC / Matra-MHS, a subsidiary of the German Daimler-Benz group and of the French Lagardère Group, signed a licensing agreement with the CEA for the transfer of DMILL to its 6" silicon foundry at Nantes. This industrial transfer is now complete. Since April 1997, DMILL is available for the construction of prototype circuits in the framework of MPCs organized by Europractice. The qualification of DMILL on the MHS production line for the mass production of mixed analog-digital circuits requiring a radiation hardness up to 10 Mrads and 1014 n/cm2, is close to be completed. DMILL will be available from October 1997 for mass production.
Performances of the industrial technology
DMILL components are guaranteed by MHS to have a hardness above 10 Mrads and 1014 n/cm2. Their low-noise performances are also monitored by MHS. Numerous circuits integrating up to 106 transistors, developped since 1993 with this technology by different laboratories for the ATLAS and CMS trackers and calorimeters, have confirmed the very good adaptation of this technolgy for constructing the hardened circuits required for the LHC experiments. DMILL has also been requested for High Energy Physics Experiments in the USA and Japan. Circuit developments with this technology have been started for space and civilian applications. To guarantee that this technology will be available for several years, TEMIC is under contract with the CEA to maintain its production until at least October 2005.
W. Fallot-Burghardt, W. Hofmann, K.T. Knoepfle, E. Sexauer,
U. Trunk
Max-Planck-Institut fuer Kernphysik
M. Cuje, M. Feuerstack-Raible, F. Eisele, B. Glass, U.
Straumann
Universitaet Heidelberg
HELIX128S-2 is the second version of a 128 channel readout chip designed for the silicon vertex and the inner tracking microstrip gas chamber detectors of HERA-B; it has been manufactured in the AMS 0.8um CMOS process.A modified version (manufactured in the DMILL process) will meet thespecifications for the LHC-B vertex detector.
The analog signal path has been completely revised with the aimof enhanced noise, power and linearity behaviour; the readout speedwas increased to 40MHz. The bias generating part (formerly on an extra chip) has been included; all settings can be programmed via a serial interface.
HELIX128S-2 can store up to 8 events (formerly 4);the number of the pipeline column storing an event is transfered as trailer of the analog data to the output.
Measurement results will be presented as well as an irradiation test of the previous HELIX128 chip.
HELIX128S-2 is the second version of a 128 channel readout chip designed for the silicon vertex and the inner tracking microstrip gas chamber detectors of HERA-B; it has been manufactured in the AMS 0.8um CMOS process. A modified version (manufactured in the DMILL process) will meet thespecifications for the LHC-B vertex detector.
The chip properties can be summarized as follows:
The analog signal path has been completely revised with the aim of enhanced noise, power and linearity behaviour:
The preamplifier employed (v. 2.1) has been further improved w.r.t.previous versions: the input transistor W/L has been increased, the pulse shape has been adjusted to minimize undershoot; specialeffort has been taken to linearize theinherently nonlinear shaper feedback network.An AC coupled differential pair stage has replaced theformer switched capacitor comparator; the output of fouradjacent comparator channels can be ANDed or ORedto adapt to different signal polarities. The pipeline readout amplifier's sensitivity to pipeline capacitancevariances has been diminished (by using a small couple capacitance);furthermore, the internal cascode has been mirrored w.r.t. nmos and pmosto achieve better linearity and a more favourable offset.The multiplexer has been given a cascaded architecture with a first stage consisting of 4x 34 channelmultiplexers running at 10 MHz and a second stage multiplexingthe 4 first stage outputs to a single lineat a readout speed of 40MHz. A permutation fan thru has been implemented to reorder the channels otherwise not written out in the correct numerical order. Finally, a low power current output buffer has replaced the former voltage buffer. The bias generating part (formerly on an extra chip) has been included into the HELIX128S-2 using an internal radiation hard reference current source; all settings can be programmed via a serial interface using three lines. HELIX128S-2 can store up to 8 events (formerly 4); the number of the pipeline column storing an event is transfered as trailer of the analog data to the output.
A token scheme has been developed to support daisy chainingof several chips. Synchronicity deviations of several chips running in parallelare detected by means of a scalable error identification circuit.
Testing of the HELIX128S-2 chip is enhanced by a built in test pulsegeneration circuit; the calibration charge injectedhas been made process invariant by relying only tocapacitor-to-capacitor ratios.
Measurement results will be presented; furthermore, the radiation hardness of the AMS 0.8 um process will be specially adressed when discussing irradiation results of the previous HELIX128 chip.
Peter Fischer
Physikalisches Institut, University Bonn, Germany
A prototype of a readout chip for multi channel detectors, like silicon strip detectors or MSGCs is presented. The chip accepts 128 digital input signals from a preamplifier / discriminator frontend at a rate of up to 80 MHz. The hit pattern is sparsified in real time and the addresses and event-ids of valid hits are stored temporarily in an on-chip FIFO. Multiple hits per event are possible. A trigger selection of interesting events can pick out only hits with a given event-id, all other hits are automatically discarded. The chip size of the presented architecture depends on the required multiplicity and on the data rate, but not directly on the trigger delay.
In most particle physics experiments, a trigger signal selects a small fraction of events only for readout. This trigger signal is available at the front end electronics which is used to read out the detector after some delay, typically some microseconds for LHC experiments. As the interaction rates are usually much higher, many events have to be stored locally in order to wait for the trigger information. In most available chips, the analog or digital hit information of many channels (up to 128) is stored in FIFO-like structures on the front end chips. The size of these chips increases therefore with increasing trigger delay, even if most events are empty. The chips can become prohibitively large if long trigger delays are needed for complicated trigger decisions.
This paper presents an alternative architecture for digital readout of multi channel systems like silicon strip or pad detectors or microstrip gas detectors. The 128 channel input patterns which can be read with a measured rate of up to 80 MHz are scanned for hits in real-time. Several hits (8 in the present implementation) can be accepted for each event. The hits are stored in on-chip FIFOs with their address and an event-id. They remain in the FIFOs until they are either selected by a trigger signal or discarded. Due to the zero supression, the data readout rate is decreased and more channels can be read per readout link. In high speed applications without trigger information e.g. in the life sciences, the reduction in readout data rate can be vital.
K. Gill*, V. Arbet-Engels, G. Cervelli, R. Grabit, C.
Mommaert, G. Stefanini, F. Vasey
CERN, CH-1211, Geneve 23, Switzerland.
J. Troska
Blackett Laboratory, Imperial College, London SW7 2BZ, England.
* corresponding author, e-mail: gill@vxcern.cern.ch
As part of the development of optical links for readout of the CMS tracking detectors, 1300 nm multi-quantum-well edge-emitting lasers and InGaAs p-i-n photodiodes have been irradiated with neutrons and 60Co-gammas. Results are presented for the radiation induced changes in laser threshold, slope-efficiency, linearity, signal-to-noise ratio, and p-i-n diode leakage current and responsivity. Based on a parameterisation of the damage effects, the damage expected under realistic LHC operating conditions is estimated. Progress and results from laser reliability studies are also presented.
All of the optical link components situated inside the CMS tracker must be both sufficiently reliable and radiation resistant to last ten years of operation. At 20 cm from the beam axis, radiation levels are expected [1] to be ~20 Mrad and ~1014neutrons/cm2. Previous irradiation studies [2], in conjunction with other criteria such as cost, and future component availability, have led to the decision [3] to base the CMS tracker optical links on directly-modulated, 1300 nm, edge-emitting lasers. The lasers are considered to be the most critical component in terms of radiation resistance and reliability since they are located inside the tracker volume. InGaAs p-i-n photodiodes are also being investigated as digital optical links will also be used to pass control signals into the tracker.
Irradiations have been carried out using neutrons (~6 MeV, up to 1015neutrons/cm2) and gammas (60Co-gamma, up to 10 Mrad). Both fully packaged (pigtailed, 8-pin DIL) and naked lasers have been tested. Fully packaged p-i-n detectors were also irradiated. Examples of the results for the change in laser threshold current and slope-efficiency due to neutron damage are shown in figures 1 and 2. The laser linearity and signal to noise performance were also measured in the lab before and after irradiation, and the spectrum was measured for the packaged devices. For the p-i-n photodiodes the leakage current and responsivity were monitored before, during and after irradiation.
It is useful to develop a working model of the radiation damage effects to predict their evolution under realistic operating conditions. For example, the laser threshold current increases due to neutron damage can be described by a simple model based on a linear build-up of active defects that decay exponentially in time. Three separate threshold current components with linear build-up and exponential decay were required to fit the data. Using these fitted parameters, an estimate has been made of the threshold current increase due to a neutron equivalent (n-eq) flux profile of 5x1014(n-eq)/cm2 over 10 years [1] (six months beam-on, six months beam-off each year). The n-equivalent flux assumes that the displacement damage of charged hadrons (mainly protons and pions) is equal to that of ~1MeV neutrons in the laser material; work is under way to calculate the actual non-ionising energy loss (NIEL) [4] due to different incident particles in InGaAsP.
Three different estimates of the laser threshold shifts are shown in Fig. 3 for 10 years in CMS (with high LHC luminosity): (a) using parameters from the fit, assuming the lasers to be always under bias so that annealing is continuous; (b) same as (a) but with lasers switched off during the LHC beam-off periods (i.e. annealing suppressed); and (c) using the results of a second fit where no annealing is allowed (t=°) for the threshold current component that had the longest time constant. The threshold shift is limited to <1.2 mA for case (a), <2 mA for situation (b), whereas for the worst-case (c) it increases at ~1.4 mA per 1014(n-eq)/cm2.
In addition to the directly observable effects of radiation damage on lasers, an experiment is planned (starting June 97) to assess the reliability of irradiated lasers. No data exists for the reliability of the tested lasers after irradiation. A batch of ~20 devices will be subjected to standard thermal and mechanical reliability tests following irradiation to a high neutron fluence (~5x1014n/cm2). Results will be presented describing the progress and findings of the reliability study.
[1] The Compact Muon Solenoid Technical Proposal. CERN Report LHCC
94-38 (1994).
[2] K. Gill et al. Proceedings of Second Workshop on Electronics for
LHC Experiments, Sept. 1996, and CERN CMS Note 1996/014.
[3] G. Hall, G. Stefanini and F. Vasey, CERN CMS Note 1996/012.
[4] G. P. Summers et al. IEEE Trans. Nucl. Sci. 35, No. 6, p. 1221
(1988).
Dachs(1*), F. Faccio(1), A. Giraldo(2), E. Heijne(1),
Jarron(1), K. Kloukinas(1), A. Marchioro(1), A. Paccagnella(2)
(1) CERN, 1211 Geneva 23, Switzerland
(2) University of Padova - INFN Padova, via Marzolo 8, I-35131
Padova, Italy
* On leave from University of Montpellier, France
Commercial submicron VLSI technologies are potentially interesting also for applications in regions of the LHC experiments where moderate radiation resistance is required. As in such regions the total dose will be accumulated over a period of 10 years, and as the machine will not operate continuously, the dose rate will be low.
In this work, we present the results of a low dose rate irradiation (0.15 krad(Si)/h) on MOS transistors in two different commercial submicron processes (0.5um CMOS and 0.8um BiCMOS). The transistors have been irradiated up to 60 krad(Si) over a period of 11 weeks in discontinuous steps of 15 hours.
The total dose deposited by radiation in the electronics for the LHC experiments will change significantly with the position, varying from tens of Mrad(Si) (inner detector) to less than 1krad(Si) (barrel muon detector) over a period of 10 years. Assuming that the LHC machine will operate about 5 months per year, such total doses will be accumulated with an average dose rate varying from 1.4krad(Si)/h to less than 0.027rad(Si)/h. During the long shut down periods annealing of the radiation effects will also occur.
The interest in commercial submicron technologies for LHC experiments comes from their better performance in terms of speed and density. Moreover, the thin gate oxide of MOS transistors in submicron technologies is inherently less sensitive to total dose effects: the failure mechanism for total dose is expected to be the leakage current due to the charge trapping in the thick lateral and field oxides. During low dose rate irradiations, the trapping and detrapping of charges in these oxides occur simultaneously, and the overall behaviour of the device is determined by the balance of the two effects. This balance is largely dependent on the particular oxide technology, but the total dose failure may be delayed by the annealing.
The purpose of this study is to evaluate the radiation performance of MOS transistors in two commercial submicron VLSI technologies (0.5um CMOS and 0.8um BiCMOS) at a low dose rate. The irradiation was performed with a 137Cs (-source (source N.2045, CERN) using a dose rate of 0.15krad(Si)/h, which is in the range of interest for LHC, up to a total dose of 60krad(Si). The exposure took place in discontinuous steps of about 15 hours followed by periods of 8 to 36 hours (exceptionally more) away from the source. Devices were constantly kept at room temperature under ìworst case biasî (Vgs=Vdd for n-channel transistors and Vgs=0V for p-channel transistors).
The devices were measured after each irradiation step, and the parameters monitored were: threshold voltage, transconductance, subthreshold swing, leakage current (source-drain), mobility. The threshold voltage of field oxide transistors was also monitored to study the possible leakage between adjacent junctions under the field oxide.
The experimental results confirm the total dose resistance of these thin gate oxides: threshold voltage shifts of less than 30mV were measured in all conditions (low charge trapping), together with subthreshold swing variations of 7mV/dec (low interface state formation) and transconductance and mobility degradation of less than 5%. The only concern comes from the leakage current of n-channel transistors and from leakage between the adjacent n+ diffusions. The source-drain leakage rises to 10pA only after ~26krad(Si) and the threshold voltage of the field transistor drops to 3V after 15krad(Si). For higher doses the source to drain leakage current might become critical for some applications (at 60krad(Si) the measured leakage is of 1nA). A comparison was made with a high dose rate irradiation and first observations point to reduced degradation at low rate. Our results, if confirmed by further investigations, would allow ICs to be functional at doses of at least 20krad(Si) in such a low dose rate environment.
A. Goldsher, V. Kucherskiy, V. Mashkova
State Scientific Research Institute Pulsar,
Okruzhnoy proyezd, 27, Moscow, Russia
The matters of designing and manufacturing an application specific semicustom array (ASSA), intended for building on its basis of an eight-channel front-end LSIC have been considered. In the capacity of the ASSA's active components there have been used n-p-n transistor structures, including ones with Schottky diodes, having a unity-gain frequency fug about 7 GHz, p-n-p vertical transistors with collectors in substrate. Passive components are resistors (high- and low-ohmic) and capacitors based on MOS structures. The ASSA contains over 7000 components, among them 1400 transistors. On the basis of this ASSA, together with the specialists of the MEPhI Electronics department, there are being conducted the works on the creation of several LSIC types for application in physical experiments within the programs of the leading Russian and foreign scientific centers.
1. The contemporary physical experimental equipment, intended, particulary, for research in the field of high energy physics, is featured ley an increase of the number of data acquisition and processing channels, reaching nowadays hundreds of thousand.
But event in this case only a relatively small variety of data processing LSICs (amplifying, filtering, discriminating an analog signal) is needed. Besides this, each physical experiment is features by its specific peculiarities, what predetermines different requirements to front-end LSICs, particularly, to shapers and comparators. Therefore, as distinct from full-custom LSICs, preferance is renderes to the ASSA, which allows by means of merely changing the lay-out of plating layers to create LSICs with account of the specific physical experiment's peculiarities and in extremely short terms.
2. The ASSA component basis includes bipolar transistor structures, since exactly they allow to create LSICs, having simultaneously a high speed, an increased dynamic range, a relatively small power consumption, high sensitivity, enhanced radiation hardness. The LSIC's active components are n-p-n transistor structures, including ones with Schottky diodes, and p-n-p vertical transistors with collectors in substrate. Passive components are resistors (low- and high-ohmic) and capacitors based on MOS structures. The working current range of standard (library) components makes up from fractions of mA to (3...5) mA. Resistor values - from tens of Ohm to tens of kOhm.
The employment of such a component basis provides simplicity, LSIC processing easiness and a high yield.
3. The basis of the ASSA manufacturing process is the planar-epitaxial technology with component isolation by a reverse biased p-n junction. The isolating diffusion of boron is thus carried out using highly doped p+-layers with preservation of boron-silicate glass before the second stage of diffusion, what allows, as distinct from commonly used modes, to reduce the stray capacitances of isolating junctions by a factor of 1,5.
The main processing peculiarities of the ASSA are as follows:
small depths of p-n junction embedding, making up fractions of a mcm, partiailarly the base width hb(0,1 mcm, what at an appropriate component lay-out and manufacturing process provides a unity gain frequency of n-p-n transistors to be about 7 GHz;
small dimensions of components, which influence on the LSIC parameters is the greatest; particularly the emitter width is 2 mcm; thereat the so-called full emitter is used; the minimum emitter size is restricted by the requirements on the collector bulk resistance rc;
simultaneous employment of a two-layer and a two-level plating based on molibdenum-aluminium or molibdenum-silicon doped aluminium;
employment of doping processes with stibium, boron and arsemcum, providing a high reproducibility of layer electrophysical parameters in a wide range of dopant concentractions.
4. The structure of the ASSA and the contents of the set of functional modules were proposed by the specialists of the Electronics department of the Moscow Engineering Physics Institute (MEPhI).
The ASSA's lay-out provides the implementation on its basis of eight channels of the most widely spread front-end modules. Each channel includes: a preamp, shaper, comparator (discriminator) and an output stage. Such a sequence of functional modules corresponds to the structure of the majurity of signal processing channels in physical experimental equipment (PhEE).
In order to reduce the influence of substrate potential variation accross the chip area there are foreseen numerous contacts with the substrate.
The utilization factor of the ASSA is not less than 70%.
5. At present on the basis of the elaborated ASSA there are conducted works together with the specialists of the MEPhI Electronics drpartment at designing a range of LSICs for PhEE, created within the programs of leading Russian and foreign physical research centers.
In accordance with the increase in the demand for front-end LSICs there can be created application specific VLSICs on the basis of the structural, technological and circuital solutions used in the elaboration of ASSA, but containing a much greater number of channels.
The work has been carried out within the framework of a project, financed by the International Science and Technology Center.
G.P. Grim, R.L. Lander
UC Davis
Results from tests of a sparsified pixel readout chip, (SPARC) will be presented. The ASIC is an 8 column by 120 row array of 48 um x192 um pixel unit cells, with each cell containing an analog front-end with pulse height discrimination for signals down to 1500 e-'s at the LHC, noise of less than 100 e-'s ENC, leakage current sink, neighbor logic, and pixel mask. Readout is accomplished using a column based readout scheme employing a simple inter-column token for bus arbitration, a current mode data bus for both analog and digital data, and end of column time stamp buffering . The SPARC chip has been laid out and fabricated in the HP 0.5 um process.
Supported by U.S. DOE.
L. HEBRARD, J.P. BLONDE, M. AYACHI, Y. HU, G. DEPTUCH, W.
KUCEWICZ
Laboratoire d'Electronique et de Physique des Systèmes
Instrumentaux
LEPSI
IN2P3-CNRS/ULP Strasbourg
France
J.P. COFFIN, F. JUNDT, C. KUHN, J.R. LUTZ
Institut de Recherche Subatomiques
IReS
IN2P3-CNRS/ULP Strasbourg
France
The circuit described here is designed to fulfill the requirements of the readout electronics for the Silicon Strip Detectors (SSD) of the ALICE experiment. It is a 128 channels chip. Each channel amplifies, shapes and stores as a voltage signal the charge deposited on a strip of the detector. An analog multiplexer allows a sequential readout of the data through an output buffer shared by the 128 channels. A slow control mechanism is used to bias accurately the different analog blocks and to control the shaping time and a test pulse generator. The relevant specifications are given in the summary.
The most restricting requirements of the readout electronics for SSD are power consumption (as low as possible, below 500uW=channel), noise (below 400e of ENC - Equivalent Noise Charge at the input), input range (10 MIPs), linearity (differential linearity below 103 ) and readout rate (10MHz). This paper described the circuit designed at LEPSI in the AMS 1:2um CMOS technology to fulfill these requirements and gives some explanations on the strategies used to reach them. It concludes with some interesting features the chip provides. The charge preamplifier and the shaper used have a structure similar to the one used in an existing 32 channel chip of DELPHI developed at LEPSI. We focused our effort on reducing power consumption to reach a value of 200uW dissipated into the preamplifier and 90uW into the shaper. This leads to an ENC of 280e- for 10pF of detector capacitance and 1.4us of shaping time. The shaping time is adjustable from 1.4us to 1.8us by tuning the feedback resistance of the shaper. The input range of 3MIPs was now increased to 10MIPs (or 286000e- ) which is also a major improvement from the previous chip. The signal delivered by the shaper is stored on an hold capacitance of 10pF which feeds an internal buffer used to drive the parasitic capacitance (Å1pF ) of the output analog multiplexer. The signal magnitude this buffer has to han- dle, the high linearity requirement and a settling time around 30ns to fulfill a readout rate of 10MHz require a power consumption of 7500uW. This value must be multiplied by 128 which is incompatible with the allowed dissipation. So, the buffers are switched on only during the readout of the corresponding channel. To reduce the noise induced by the on/off switching, the internal buffers previous and next to the channel under reading are also switched on. So, during the readout cycle, four buffers are switched. Assuming a readout every 1ms during 128 x 0.1us leads to a mean power consumption of 3uW per channel. These internal buffers feeds the output buffer shared by the 128 channels. This single ended buffer can drive a link with a caracteristic impedance of 100½ in parallel with 20pF . Here again, the restricting requirements on signal magnitude, linearity and settling time ask for a dissipated power of 35000uW. So, the buffer is switched on only during the readout cycle. This leads to a mean power consumption of 3.5uW per channel assuming the previous readout conditions. When switched off, the buffer output is at a high impedance. This allows the daisy-chain of 12 chips on a detector module. A slow control mechanism allows to control the biasing of all the analog blocks. It controls also a pulse generator used to test the circuit with different impulse levels. The JTAG and I2C protocols have been studied to design this slow control and we will choose the best one according to the end cap designer preference. We chose to implement the three most perturbing logic signals (the readout clock, the hold signal and test asking signal) by use of LVDS (Low Voltage Differential Signal) levels to reduce the noise they induce. The circuit will be sent to manufacturing at the end of June and we expect to test it on september.
C. Dachs(1), F. Faccio(1), A.Giraldo(2), E. Heijne(1), P.
Jarron(1), A. Marchioro(1), E. Noah?, A. Paccagnella(2)
1) CERN-ECP
2) University of Padova
An investigation of the total dose behaviour of three different commercial submicron technologies has been carried out. Existing reports on such technologies and a set of theoretical studies have reported that such technologies will become more immune to total dose effects, mainly through the introduction of very thin gate oxides. We present a set of comparative measurements carried out on test structures irradiated up to 1 Mrad (SiO2) in 0.5, 0.35 and 0.25 um CMOS conventional transistors and also on special "enclosed" structures, laid out to overcome leakage current problems. The results obtained so far are very encouraging and substantially confirm the expected trends; very low voltage shifts have been measured; the new layout techniques applied, despite an increase in area used, also shown an effective technique to solve leakage current problems.
This work investigates the total dose behaviour of different submicron VLSI technologies irradiated with X rays. As CMOS processes are scaled down in the deep submicron regime the gate oxide thickness is decreased to dimensions well below 100 Å. Theoretical studies and early measurements have predicted that, because of the reduced charge trapping in the gate oxide volume, radiation should induce smaller threshold voltage shifts. In addition, these advanced technologies will likely modify the field oxidation process from LOCOS to shallow trench isolation (STI). An objective of this study is to verify that no negative effects arise due to this new step. These issues have been studied on three different state of the art technologies and the results obtained are described in this paper. We propose that conservative design rules and special layout techniques should be used to overcome other potential radiation effects which are not addressed in commercial technologies.
Three different standard commercial technologies have been studied : 0.5 um CMOS with 100 Å gate oxide thickness and LOCOS isolation, 0.35 um CMOS with gate oxide thickness of 70 Å and LOCOS isolation and finally 0.25 um CMOS with gate oxide thickness of 55 Å and STI. Test structures were obtained from three different manufacturers and three high volume process lines currently in use for advanced memory and logic integrated circuits. We have used NMOS devices laid out in a standard fashion as well as especially designed transistors (only for 0.5 um) consisting basically of "enclosed" structures i.e. transistors without bird's beak. Such structures eliminate the potential leakage path between source and drain otherwise present at the edge of the conventional transistors.
The devices were irradiated up to 1 Mrad (SiO2) - some up to 3 Mrad - with X rays (10 keV) at a dose rate of 4 krad/min. The annealing results were obtained after 1 week at 100 °C consistently with the recommended ESA procedure. ( A consistent set of results was obtained also with a conventional Co60 irradiation up to 1 Mrad but these results are not reported in this paper.)
The trend expected from the theoretical studies for threshold shift was confirmed by our measurements. After 1 Mrad the 0.5 um technology shows the largest Vth shift: before annealing between 140 and 180 mV for NMOS devices. In similar conditions the 0.35 um technology has only between 40 mV and 150 mV. And the best performance was given by the 0.25 um technology which resulted in a voltage shift of less than 10 mV. Annealing results, transconductance characteristics, as well as measurements on PMOS devices are detailed in the paper.
The leakage current results of an NMOS transistor irradiated at 1 Mrad suggest that the new STI isolation technique has no negative impact. For the 0.5 um LOCOS technology we measured a leakage of 10 to 100 mA. For the 0.35 um LOCOS similar results were obtained. Surprisingly the 0.25 um STI technology leakage current was lower, between 1-10 mA. We stress that in the latter case the technology also enjoys a lower VDD voltage.
Special NMOS devices were drawn as enclosed structures in the 0.5 um technology to assess the effectiveness of such layout technique. While such structures considerably increase the area necessary for a given cell we have shown that the leakage problem could be solved without resorting to special technological steps. For an NMOS device of nominal 10/0.5 um dimensions we have measured a leakage current of 100 mA for the open device and only 10-5 mA for the enclosed version.
The results are very encouraging with respect to total dose behaviour and are consistent with the expected theoretical trends, but more extensive studies will be required to fully confirm these preliminary measurements. Full confirmation of the applicability of deep submicron technologies in the LHC environment still needs extensive studies in areas such as single event latchup and single event upset susceptibility. Noise characteristics and applicability of these technologies for analog applications also have to be better understood.
Christophe de La Taille, V. Radeka
At the beginning of this year, most decisions have been taken on the front end electronics of the ATLAS liquid argon calorimeter and have been written in the Technical Design Report. The talk will review briefly the various elements of the front-end : calibration, preamps, shapers... from the point of view of design, measured performance and implementation.
S. T. Liu and T. Bradow
Honeywell Solid State Electronics CenterPlymouth, MN 55441, U. S. A.
This paper describes radiation response/performance of a further hardenedCMOS technology by characterization of the threshold voltage shifts andleakage currents as a function of total dose. The threshold voltage shiftsof the top channels were less than 170 mV at 50 Mrad for both NMOS and PMOStransistors. No radiation induced leakage currents were observed over theentire range of radiation test (100 Krad to 50 Mrad). This data furtherdemonstrates the suitability of this technology for LHC experiments.
A recent paper describes a radiation hard CMOS technology in which the NMOSwere hardened to 25 Mrad with little performance degradation [1]. Althoughthe PMOS transistors were hardened to 25 Mrad, a significant threshold shift(Å550 mV) caused degradation in transconductance affecting gain andnoise performance. This paper describes further radiation hardening ofpartially depleted 0.7 um SOI CMOS technology with emphasis on the PMOStransistors fabricated on full dose SIMOX (Separation by implantation ofOxygen) wafers with an oxygen ion dose of Å1.7x10^18/cm^2 at 200 KeV. TheSIMOX wafers used in this study have a buried oxide thickness ofapproximately 370 nm and a silicon thickness of approximately 230 nm.
In this CMOS technology N and P wells are implanted to create partiallydepleted N+ polysilicon gate surface channel NMOS and buried channel PMOStransistors. Both oxide and junction device isolation are used within wells,and oxide isolation is used between N and P wells to maximize layout densityand minimize gate parasitic capacitance. It is further improved by usingplanarized shallow trench isolation self-aligned to active areas andtransistor body. In addition to the top channel conduction of a SOItransistor, parasitic conduction paths may be induced by the irradiationeffects on the NMOS back channel transistor associated with the buried oxideand the top and back field transistors associated with junction isolateddevices. These parasitic components have been hardened to reduce radiationinduced increases in standby currents. The gate length of the SOI CMOStechnology is effectively 0.55 um. The gate polysilicon and source/drainareas are silicided using titanium salicide processing.
Individual CMOS transistors were fabricated for this study. The output andinput characteristics of the individual transistors were measured with an HP4145 parametric analyzer prior to any radiation testing. Total dose radiationhardness is assured by testing process monitor devices using an ARACOR model4100 X-ray source to 50 Mrad. The top channel threshold voltage shift of NMOStransistors subjected to the on-gate irradiation bias was less than 120 mVover the entire range of 50 Mrads. No radiation induced leakage currentswere observed for NMOS transistors subjected to any irradiation biasconditions including the worst case of back channel conduction (pass-gateirradiation bias). The top channel threshold voltage shift of PMOS transistors subjected to theoff-gate irradiation bias has been improved to < 170 mV at 50 Mrad, a valuetypically observed at Å2 Mrad. No radiation induced leakage currents wereobserved for PMOS transistors subjected to the worst case irradiation bias. The improvement assures better performance of radiation hard SOI CMOS devicesfor LHC electronics applications.
References:1 S. T. Liu, C. S. Yue, T. Bradow, and W. C. Jenkins, "Total dose hard 0.8um SOI CMOS Devices", Proceedings of the First Workshop on Electronics forLHC Experiments, pp. 33-37 (1995).
K. Kloukinas, C. Ljuslin, A. Marchioro, P. Moreira, G.
Stefanini, F. Vasey
CERN/ECP-MIC
All complex data acquisition systems such as those which will be used for the LHC experiments require not only a data path for the read-out of analog or digital data, but also fairly sophisticated so called ìslow control systemsî for the more mundane functions, such as control of the status of the detector, front end calibrations, monitoring of environmental parameters, downloading of parameters and distribution of critical timing information and their adjustments.This paper describes the architectural design of such a system optimized for the CMS inner tracker detector. This design was constrained by the heavy demand on reliability, radiation hardness, cost and minimization of number of different types of components. The resulting design is a careful mix of a long distance optical network with a local electrical network. The architecture, functionality, protocols and some of the key components used in these networks will be described.
The most difficult constraint presented to system designers by the LHC environment is the requirements to have radiation hardened components in many parts of the electronics embedded on detectors. This requirement rules out the use of almost all standard commercial components and modules and forces the design of an ad-hoc set of components capable of surviving after quite massive doses of ionizing radiation. Even though ASIC design has become relatively popular in the HEP community, one has to resist the temptation to build too many different components, as each ASIC demands a large investment in man-power and resources. The requirements demanded by the CMS tracker detector are typical of many other detectors, but the high number of channels, the demand for high reliability and the constraint on cost have significantly influenced the architecture of the system presented in this paper. Some critical choices made fairly early in the design were the re-utilization of the opto-electronics components developed for the data read-out and the splitting of the fairly large control network in a two-layer hierarchy, with long distance, medium speed optical links followed by local low-cost, low speed electrical connections wherever possible on the detector. Using this hierarchy, only two major components where recognized, therefore minimizing the design effort. A fully digital network controller, used for the management of the control networks and a custom PLL used for the regeneration and timing adjustments of the clock and trigger signals. Some other auxiliary circuits, such as drivers and level converters are also unavoidable, as basic RC laws are difficult to be eliminated, but clearly require a reasonably low design effort. All complex network elements, such as control microprocessors and related software are housed in the safe control room and can be built with standard parts.The resulting architecture offers a good compromise between cost and performance, where performance is defined as a fuzzy function of functionality, reliability and flexibility. The developed architecture is a posteriori rather generic, and it could be applied also to other detectors.In the effort to minimize design support, debugging, long-term maintenance and documentation efforts, the protocols used were also largely inspired from commercial networks and are described in the paper.
O.Martin, B. Dinkespiler, M. Jevaud, C. Olivetto,
E.Monnier, M.Wielers, S. Tisserant
Centre de Physique des Particules de Marseille, CPPM
IN2P3-CNRS et Université d'Aix-Marseille II, Marseille, France
M.L Andrieux, J. Ballon, J. Collot, A. Patti
Institut des Sciences Nucléaires, ISN
IN2P3-CNRS et Université de Grenoble I, Grenoble, France
L.O. Eek, A. Go, B. Lund-Jensen, M. Pearce, J. Söderqvist
Royal Institute of Technology, KTH,
Physics Dept. Frescati, Stockholm, Sweden
J.P. Coulon
Laboratoire de l'Accélérateur Linéaire, LAL
IN2P3-CNRS et Université de Paris XI, Orsay, France
Our group has been concentrating its efforts in the last years [1] [2] on analogue optical solutions to the read-out requirements of the ATLAS liquid argon electromagnetic calorimeter. We now present results from a demonstrator of a 64 channel analogue optical link.
Signals from outside the calorimeter cryostat must be transmitted to the counting room 70 metres away with a 10-bit dynamic range and minimal power consumption.
Arrays of VCSEL diodes, already known [3] as reliable in terms of radiation hardness and life time, are used as emitters. The receiver is based around a custom-designed PIN photodiode array. Thorough laboratory tests of the entire demonstrator link are discussed.
[1] Analogue optical links for the liquid argon calorimeters, B.
Dinkespiler et al, Proceedings of the first workshop on electronics
for LHC experiments, Lisbon, CERN/LHCC/95-56
[2] Analogue optical links for the front-end read out of the ATLAS
liquid argon calorimeter, B. Dinkespiler et al, Proceedings of the
second workshop on electronics for LHC experiments, Balatonfured,
CERN/LHCC/96-39
[3] First reults of a comprehensive life time test of irradiated LEDs
and VCSELs, J.Beringer et al, Proceedings of the second workshop on
electronics for LHC experiments, Balatonfured, CERN/LHCC/96-39
P.O'Connor*, G. Gramegna+, P. Rehak*, F. Corsi+, C.
Marzocca*
* Brookhaven National Laboratory, Upton, NY 11973 USA
+ Politecnico di Bari, Dipartimento di Elettrotecnica ed Elettronica,
via E. Orabona 4, 70125 Bari, Italy
An ultra low noise preamplifier for small capacitance (200fF), low leakage current solid state detectors has been designed and fabricated in two different CMOS technologies. The circuit is suitable for application in X-ray detection systems and its performances in terms of gain linearity and equivalent input noise charge (ENC) compare favourably with present state-of-art circuits. A linearity error less than 0.1% up to 1.8fC input charge and an ENC of 13e- rms at 2.4us shaping time have been achieved by adopting original circuit solutions for the feedback scheme of the charge sensitive amplifier, which has been realized with a P-channel MOSFET biased in the weak inversion region. One of the two version of the circuit include also an integrated shaper realized by a MOSFET-C approach. The general philosophy of the circuit along with the main experimental achievements will be reported in the paper.
A large number of applications require extremely low noise detection systems, based on small capacitance and low leakage current detectors. [1,2].
The charge sensitive preamplifier (CSA) [3, 4, 5] is widely used at the front-end due to its low noise performance and gain insensitivity to detector capacitance variations. The input charge pulse is integrated onto a feedback capacitor Cf. A feedback resistance Rf provides the DC path for the detector leakage current and at the same time avoids the saturation of the CSA by preventing the continous increase of the charge integrated on Cf,due to successive events.
For ultra low noise applications, the order of magnitude of the detector leakage currents is 1-10pA, therefore the value of the damping feedback resistor should be extremely high in order to preserve the noise performances achievable by the detection system.
The only practical way to achieve the 5-50 Gohm feedback resistance required to avoid extra contribution to the input parallel noise is to use the drain-source equivalent resistance of a MOSFET Mf biased close to the weak inversion region. Since we have a very small total parallel noise contibution in input, the shaping time can be chosen long enough to reduce at reasonably low level the series noise contribution. This is possible because of the absence of strict speed requirements. In this way the only remarkable input noise component is represented by flicker noise, which is not affected by the shaping time and is strictly related to the technology adopted. Therefore the matching conditions between the gate capacitance of the input transistor and the detector one will be chosen to minimize the flicker noise contibution.
The feedback and the parasitic capacitances should be kept as small as possible [6,7] and the input transistor is a P-channel device, which shows better flicker noise characteristics as compared to the N-channel counterpart. Mf is a P-channel transistor as well, to achieve a resistance three times larger than the one achievable with an N-channel device of the same size.
The exponential characteristics of the feedback MOSFET would affect remarkably the linearity of the system, as the output swing results in hundreds millivolts. A good compromise must be found between the capability of the feedback transistor to absorb a large spead of leakage values without bringing the CSA in saturation and the linearity requirements which would call for a constant VGS of the feedback device Mf. We propose a feedback scheme with a linear voltage divider between the output of the CSA and the source of the feedback transistor which attenuates the VGS voltage swing significantly, improving the linearity of the CSA gain while still ensuring a good range of acceptable leakage currents. Moreover, the multiplied decay time of the CSA response to a current pulse, avoids the need of a pole-zero cancellation before signal shaping, as decay time of the order of ms are easily achieved [8,9], and further improves the linearity of the CSA, thanks to the increased ratio between the main poles of the circuit.
A self-adaptive bias circuit for the feedback transistor Mf ensures a stable and reproducible value for the associated resistance, tracking the statistical threshold variations, which can reach +-100mV in a typical CMOS process [10].
The circuit was fabricated in two different foundries: I) HP 1.2um and II) AMS 1.2um in order to compare the flicker noise behavior of the two processes.
The response of the CSA to a charge pulse is almost insensitive to temperature variations, and the change of the Rf is less than 20% when changing temperature by 100C.
The linerarity error which affects the voltage/charge conversion gain of the AMS version of the preamplifier as a function of the input charge is less than 0.1% up to an input charge of 1.8 fC.
The measure of the FWHM of the pulser peak for the 55Fe spectrum has been performed at -70C and 3.6us shaping time. The value achieved is 111 eV, wich corresponds to an input equivalent noise charge of 13 electrons rms.
In the AMS version of the circuit a MOSFET-C second order shaper has been cascaded to the CSA. A parallel Mx-Cx network performs the cancellation of the tail of the CSA output signal produced by the feedback MOSFET Mf, according to a solution successfully adopted in [10]. Two MOSFET-C stages, based on the same folded cascode amplifier used for the CSA, introduce two coincident poles. Experimental results about the shaper will be presented at the conference.
The excellent performances achieved by the proposed front-end circuit in terms of noise and linearity make the solutions adopted particularly attractive for applications at LHC in which accurate charge measurements will be required.
REFERENCES:
[1] W. Chen, H.W. Kraner, Z. Li, P. Rehak, F. Hess, IEEE
Transaction on Nuclear Science, vol. 41 n.4, pg 941-947 August
1994.
[2] B. Ludewigt, J. Jaklevic, I. Kipnis, C. Rossington, H. Spieler,
IEEE Transaction on Nuclear Science, vol. 41 n.4, pg 1037-1041 August
1994
[3] Gatti, Manfredi, Nuovo Cimento
[4] Radeka, Ann. Rev. Nucl. Part. Sci. 1988. 38 217-77
[5] E. Beauville et al. "AMPLEX, a Low-Noise, Low-Power Analog CMOS
Signal Processor for Multi-Element Silicon Particle Detectors", Nucl.
Instrum. and Meth. A288 (1990), 157-167
[6] Z. Y. Chang, W. Sansen, "Low Noise Wide-Band Amplifiers in
Bipolar and CMOS Technologies", Kluwer Academic Publishers, 1991, Ch
5.
[7] W. Sansen, IEEE Transaction on Circuits and Systems, 37(11), Nov.
1990, 1375-1382.
[8] R. Boie, A. Hrisoho, P. Rehak, "Signal Shaping and Tail
Cancellation for Gas Proportional Detectors at High Counting Rates",
Nucl. Instrum. and Meth. 192 (1982), 365-374.
[9] P. O'Connor, G. Gramegna, P. Rehak, F. Corsi, C. Marzocca, "CMOS
Preamplifier with High Linearity and Ultra Low Noise for X-Ray
Spectroscopy" IEEE Nuclear Science Symposium, Anheim (CA), Nov.
1996.
[10] G. Gramegna, P.O'Connor, P.Rehak, S. Harts, "CMOS preamplifier
for Low-Capacitance Detectors" Nucl. Instrum. and Meth., to be
published.
A.Holmes-Seidle, J.Matheson, S.Watts
Brunel University, Uxbridge UB8 3PH
G.Hall, M.Millmore, M.Raymond
Imperial College, London SW7 2BZ
APV6 chips have been gamma irradiated using a 60Co source in order to confirm the radiation hardness expected from measurements on individual transistors and on the APV5 chip. The additional capabilities of the APV6 are outlined, the test system described and detailed measurements are presented of noise, power consumption and pulse shape following irradiations of up to 15 Mrad. We believe that full functionality of the chip will be preserved under LHC operating conditions.
Experiments at the forthcoming LHC will place stringent requirements on electronics used in the tracking of charged particles. Devices will be exposed to radiation levels around 10Mrad and 1014 particles cm-2 over their lifetime. Nevertheless, low noise operation must be preserved, timing resolution must remain adequate and power consumption per channel must be kept to a tolerable level .
The RD20 Collaboration has developed a front-end readout system based around the APV6 chip [1]. Each channel of the APV6 contains a preamplifier, shaping amplifier and a memory into which samples are written and stored until a first level trigger decision is taken. Noise and power consumption are optimised by using a pulse shaping time constant close to 50ns, whilst sufficient timing resolution is achieved using the deconvolution technique. This architecture is shared with the APV5 chip, which has been demonstrated to perform adequately up to a dose of 15 Mrad [2].
The APV6 is, in addition, equipped with a slow control interface using the Phillips I2C bus. This allows setting of operational bias conditions and control of the on-chip test pulse system. Since deconvolution is implemented for a particular pulse shape, the internal test pulse system has been designed to allow mapping of the pulse shape by sweeping the test pulse delay relative to the clock.
The APV6 chips were glued and wire bonded onto fineline PCBs, nine APV6 inputs being available for direct application of test pulses. The APV6 board was interconnected to three peripheral PCBs, which included unity gain buffering of the output signals for testing. For irradiation, similar boards were constructed omitting radiation-sensitive components and the signals from the APV6 were monitored using an oscilloscope outside the irradiation cell.
The readout system was based on a VME crate controlled by Macintosh computer running LabView software, via a National Instruments PCI to VME interface. A VI2C VME to I2C interface card [3] performed the slow control, whilst clock and trigger lines were supplied using a SEQSI [4] multi-channel programmable pulse generator. The APV6 analogue output was amplified and passed to a CMS FED ADC module [5], which was read out over the VME bus. A repetitive sequence was used in which the chip was reset, triggered and read out using a 40Mhz clock.
60Co gamma irradiations were performed up to 15Mrad, using a silicon photodiode for dosimetry. After each irradiation step, the pulse shape was mapped using the internal calibration system, averaging many calibration pulses at each delay value.The noise of all channels was determined by a statistical analysis of the data accumulated. Of those input channels available externally, some were loaded with capacitors to ground, to allow determination of noise performance versus load capacitance. After each set of measurements, the bias generator settings were re-tuned and the chips re-measured before the beginning of the next irradiation. Power consumption as a function of clock frequency was also measured.
Detailed measurements have been made of the performance of the APV6 chip under gamma irradiation up to 15Mrad, including noise, power consumption and pulse shape. We believe that full functionality will be preserved under LHC operating conditions.
[1] M.French et al., Proceedings of the Second Workshop on
Electronics for LHC Experiments, CERN/LHCC/96-39, Oct.1996
[2] M.Raymond and M.Millmore, Results of Irradiating the APV5 Chip,
CMS TN/1996-009
[3] VI2C designed by E.Murer, ECP Division, CERN
[4] SEQSI designed by M.Morrissey, Rutherford Appleton Laboratory
[5] FED designed by System Design Group, Rutherford Appleton
Laboratory
P. Moreira, T. Vaaraniemi, A. Marchioro and T. Toifl
An ASIC consisting of an array of four linear laser drivers has been designed, fabricated and tested. The IC is dedicated to the transmission of analogue data from two of the CMS central tracker detectors to the front-end digitizer cards.
The ASIC drives a laser diode converting the analogue data produced by the front-end APV chip into an amplitude modulated optical signal. Each driver contains a programmable current source allowing independent biasing of any of the four laser diodes in its linear region of operation. The laser driver was designed in an 0.8um BiCMOS process. The driver has been successfully tested both electrically and in combination with a laser diode/optical receiver. Measurement results are reported.
An ASIC consisting of an array of four linear laser drivers has been designed, fabricated and tested. The IC is dedicated to the transmission of analogue data from two of the CMS central tracker detectors - gas and silicon microstrip - to the front-end digitizer cards.
On the occurrence of a first level trigger, the analogue signals processed by two APV front-end ICs are multiplexed (by a dedicated ASIC) and sent to a single optical channel at a rate of 40 MS/s. Since each APV IC serves 128 channels, a single optical fibre link is used to transmit data from 256 channels. The analogue data, coded as an amplitude modulated signal, is converted by the laser-driver and the laser diode in an amplitude modulated optical signal. In order to achieve the required signal-to-noise ratio the electrical-to-optical conversion has to be made with a minimum of noise and non-linear distortion. An objective for the whole communication channel is to achieve a performance equivalent to that a 7-bit digital system. Each link element should thus exceed this performance. The goal fixed for the laser driver was to attain 8-bit equivalent performance. This requirement converts in to the following major specifications:
* Dynamic range: 8 bits
* Integral non-linearity: < 1%
* Equivalent input noise: 1 mV ( equivalent of 1 LSB/3)
* Settling time: < 10 ns to within 1% of the final value
* Crosstalk: < 0.3%
Since one of the goals of the project was to include four drivers in the same IC, each driver was designed as a full differential circuit. In this way, the sensitivity to power supply noise is minimised and the amount of power supply noise generated by each driver in its neighbours is reduced. Each driver contains a programmable current source allowing independent biasing of any of the four laser diodes in its linear region of operation. This feature is necessary to compensate for device to device variations, device ageing, and device performance degradation due to radiation. The programmable current sources can be independently programmed via an I2C interface. Each driver can be individually disabled to reduce power consumption in an unused or defective channel. The laser driver was designed in a standard commercial 0.8um BiCMOS process and its dimensions are 1.9 mm x 2.9 mm.
The laser driver has been successfully tested both electrically and in combination with a laser diode/optical receiver. The measured Integral Non-Linearity is less than 0.42 % for input voltages less than ± 400 mV - the specified operating range. Pulse response tests show that the crosstalk between two channels is less than 0.27 % for input signals with transition times up to 5 ns. The measured equivalent input noise is 1.8 mV and 4.4 mV for minimum and maximum laser diode bias current respectively.
Christian Neyer
GSI Darmstadt/Germany e-mail: C.Neyer@gsi.de
A discriminator for precise time measurements has been integrated in a bipolar chip. It works with two thresholds and finds the beginning of a pulse by linearly extrapolating the leading edge. This is used for compensating fluctuations of the pulse shape. The remaining walk at the output is 30 ps peak to peak when the rise time at the input is varied between 250ps and 1ns. For amplitudes between 50mV and 250 mV, this is 40 ps peak to peak. A chip of this kind is foreseen for Time of Flight measurements in ALICE.
Time of Flight will have to be measured with an accuracy of less than 50ps rms in the Alice detector. Pestov spark chambers are foreseen as a relatively cheap but precise detector for this purpose. They produce signals with rise time between 250ps and 1ns and amplitudes in the range from 50mV to 500mV. However, useful time information is contained in the beginning of the signal only.
Several methods are possible to determine the beginning of a pulse. The technique used here, works with two thresholds. When they are passed by the input signal, a linear extrapolation to the baseline is performed. The intersection point found in this way is a good measure for the beginning of the pulse. Fluctuations in rise time or amplitude of the detector signal can be compensated in this way.
A discriminator that works in the way described, was built at GSI in '95 already. The discrete circuit was presented during the first and the second workshop on electronics for LHC experiments. The time resolution 80 ps rms was achieved for a system that included Pestov spark chambers, this discriminator and TDCs in a test beam.
In order to allow for a mass production in the future and for decreasing size, power consumption and costs of the circuit, it was integrated into a chip. This was the first chip designed at GSI. The process chosen is a 0.8um bipolar process with a transit frequency = 27 GHz. A semi custom technique was used. NPN transistors of different size, lateral PNP transistors, Schottky diodes, 2 types of poly silicon resistors, NiCr resistors, capacitors and 3 layers of metalization were available. The design software was rented from the chip manufacturer.
The size of the die is 1.8mm*1.9mm and it contains 36 pads. Beside the pins for basic functions, such as power supply, inputs and output, several pads are used for adjusting different parameters on the chip. Additional pins exist for enabling and disabling parts of the circuit and for accessing test structures, also placed on the die.
The measurements performed in the electronics laboratory resulted in a remaining time walk at the discriminator output of 40 ps peak to peak when the amplitude at the input varied between 50mV and 250 mV. The walk was 30 ps peak to peak when the rise time changed between 250 ps and 1 ns. The power consumption of the chip was 150 mW at nominal adjustments.
S. Panebianco, V. Russo, S. Reito
Dipartimento di Fisica dell' Universita' and Sezione INFN, Catania,
Italy
Two full custom Analog Memories have been designed, realised and now are under test. These Memories have been realised in view of the final design of the readout system for the Silicon Drift Detectors (SDDs) that will be used at LHC in ALICE detector as part of the Inner Tracker.
The two memories have been integrated in double poly, double metal AMS 0.8 un CMOS. The memories have input and output swings of 3 V, a linearity better than 0.1% and a pedestal variation from cell to cell less than 1 mV.
The main aim of the two design is to study the properties of the basic cell of the memory and to design a layout with the minimun size, very low crosstalk and power dissipation, a very good linearity and high input/output swings.
The two Analog Memories have been designed as arrays of switched capacitors with only one OTA amplifier to read the cells. While the first one (ADeLine1) is only one channel of 8 cells, the second one is organized as 8-channel, 256-cell (ADeLine2).
Each cell of the array consist of a poly-poly capacitor and a NMOS switch. The cell is designed in such a way that the cell pedestals and the turn-off time of the switch is independent on the input signal level. With this architecture the Analog Memory shows low cell-to-cell offset and small sampling time variation across a channel.
The Analog Memory must continously sample the analog signals coming from the detector and store all the datas. It must be addressed in a sequential mode during the write phase, writing all the channels of a column simultaneusly. The datas in the memory are sparse: then only the cells containig non zero data shall be read in a random mode, that is only one cell a time. For this reason only one OTA amplifier is necessary to read the cells, than obtaining a substancial decrease of power dissipation and chip size.
The addressing system in Analog Memory is based on two dinamic Up-Down Ring Shift Register (RSR) designed full custom for size reduction, high speed performance and power dissipation. The direction of the RSR is controlled by an Up-Down signal. Two enable signal, Write Enable (WE) or Read Enable (RE) select the appropriate operation.
Both the memories have been integrated in double poly, double metal AMS 0.8 um CMOS. ADeLine1 is a 0.7 mm x 1.1 mm size chip while ADeLine2 is 4.1 mm x 2.2 mm. ADeLine2 chip works up to 1 MHz as in write as in read phase with a power dissipation of 8 mW/ch. The write speed of ADeLine1 is increased up to 40 MHz with a power dissipation of 3.5 mW. Both the memories have input and output swings of 3 V, a linearity better than 0.1% and a pedestal variation from cell to cell in one channel less than 1 mV.
James L. Pinfold
University of Alberta.
A brief introduction to the ATLAS liquid Argon Calorimetry Switched Capacitor Array readout system downstream of the shaper chips will be given. The talk will concentrate on the development of a Field Programmable Gate Array implementation of the SCA Pipeline Controller that enables the SCA readout system to function as an essentially deadtimeless Random Access Analog Memory. The system prototyped so far is capable at running in excess of 40 MHZ - in accordance with LHC requirements.
We are working on the frontend readout for the ATLAS liquid Argon calorimetry. We, in conjunction with Nevis Labs and Orsay/Saclay, are developing a Switched Capacitor Array readout system. Although we had designed and tested a complete system our responsibility is now the design and fabrication of a pipleine controller chip that keeps track of the addresses of all the stored info. and allows our system to function as a Random Access Analog Memory. A novel feature is the use of the latest FPGA technology which in our implementation can run according to full LHC specifications (eg >40 MHz).
A. Marchioro - CERN/ECP-MIC, marchior@sunvlsi.cern.ch
P. Moreira - CERN/ECP-MIC, pmoreira@sunvlsi.cern.ch
P. Placidi - CERN/ECP and University of Perugia,
placidi@sunvlsi.cern.ch
The CMS central tracker will use clock and trigger signals derived from the general Timing and Trigger Control (TTC) system developed within the RD-12 project. These signals are transmitted encoded in a 40 MHz square wave that simply presents a missing pulse when a trigger occurs.This paper describes the design of a dedicated low jitter PLL-Delay ASIC optimized for this application. Design requirements and preliminary simulation results are reported. Special emphasis is put into the optimization of several blocks of the PLL; furthermore the description of a mathematical model used for the optimization of the circuit is detailed.
The front end electronics in LHC experiments operates synchronously to a master 40 MHz clock distributed from a single central source. The CMS tracker uses a distribution scheme based on a simplified version of the TTC system developed to this purpose within the RD-12 collaboration. Clock and trigger information is encoded in a single signal, where a 40 MHz square wave is used for the clock and a missing pulse in this sequence represents the presence of a trigger event. Such scheme minimizes the bandwidth requirements on the transmission medium. To recover the full original clock and trigger from this signal, a dedicated PLL-Delay chip has been designed. The application also requires that the phase of these signals be adjustable in steps of around 1 ns for precise bunch-crossing identification.A classical PLL design with digital phase detector control has been adapted to this application. In order to minimize the clock jitter due to the missing pulses protocol, a special phase detector is used. A constant amplitude, differential Voltage Controlled Oscillator is also used to minimize noise and power supply dependence of the oscillator frequency. In this design, the VCO provides also the function of a delay line, where a phase shifted clock is extracted for external use. Finally, a special digital calibration circuit was used to minimize dependence on process parameter variations and to allow auto-calibration of the devices.The chip will eventually be fabricated in a rad-hard BiCMOS technology. This paper describes the design of a prototype version in a conventional 0.8 um BiCMOS, 3.3V, dual metal process.The design of the ASIC including expected characteristics will be described; moreover, a description of the mathematical models used for the simulation and study of the stability characteristics of the PLL will be given.
M.French, L.L.Jones, P.Murray
Rutherford Appleton Lab, UK
M.Raymond, G.Hall
Imperial College London, UK
The APV6 is the final prototype of the rad-hard 128 channel front end readout chip for the CMS silicon tracker at LHC, fabricated in the Harris AVLSIRA process. Each channel comprises a low noise amplifier, a 160 cell analogue pipeline and a further signal processing stage which can implement a deconvolution operation to achieve single bunch crossing time resolution. The data from all channels is transmitted on a single serial output via a high speed analogue multiplexer. The chip incorporates necessary system features, including on-chip bias and calibration pulse generation.
The CMS inner tracker contains approximately 107 channels implemented in silicon and gas microstrip (MSGC) technologies. To achieve robustness against interference and other common mode effects analogue readout has been adopted, the data being transmitted optically for external digitization. Slow control and monitoring of the detector and internal electronics will be implemented digitally via separate optical links.
The Harris AVLSIRA bulk CMOS process meets the radiation hardness requirements for electronics located within the tracker volume. Prototyping of test structures and readout electronics in this process has been underway for several years, culminating in the APV6 which is the final prototype of the readout chip for silicon microstrips in CMS. A modified version of the APV6 will be used for readout of MSGCs.
The APV6 consists of 128 amplifier, pipeline and further analogue signal processing (APSP) channels followed by an analogue multiplexer. The amplifier output pulse (50 nanoseconds peaking time) is sampled continuously at 40 MHz into the analogue pipeline which is 160 elements deep. The depth of the pipeline accomodates the level one trigger latency and also provides buffer locations for triggered events awaiting readout. Triggered events are read out at a speed compatible with multiplexing the data from two chips onto one optical fibre. The APSP can operate in either Peak or Deconvolution mode. In Peak mode one triggered sample/channel (the peak value of the the amplifier output pulse) is multiplexed out, which can be used at low luminosity to give better noise performance. In Deconvolution mode the output is a weighted sum of three sequential samples from the pipeline. Deconvolution mode can be used at higher luminosities to achieve single bunch crossing timing resolution at the expense of higher noise since the deconvolution operation effectively reshapes the amplifier output pulse shape to one that peaks at 25 nanoseconds and then returns rapidly to the baseline, thus eliminating pile-up.
System requirements dictate that each optical fibre transmits data from two APVs. To achieve this the APV multiplexer runs at 20 MHz and the output data streams from two chips are multiplexed at 40 MHz by an external circuit onto one optical channel.
The APV6 incorporates necessary features for control and monitoring of a large and complex system. Each chip requires a 40 MHz clock and a level one trigger line. A two wire slow control interface has been implemented which allows bi-directional communication with every chip in the system using an industry standard protocol, allowing individual tuning of bias currents and voltages (via on-chip DACs). The slow control interface is also used to programme the operational mode of the chip, to diagnose error conditions arising, and to control calibration circuitry for detailed mapping of the analogue pulse shape.
The APV6 is a fully functional chip for analogue readout of silicon microstrip detectors at LHC, incorporating features which will allow control and verification of performance throughout the lifetime of the experiment. This paper presents the design and measured performance in detail.
G. Mazza
INFN sezione di Torino, Italy
A. Rivetti
Politecnico di Torino, Italy
We present two schemes for 2-stage transimpedance amplifier based on the active feedback principle. The first one is a current amplifier followed by a transimpedance amplifier. The second one is a transimpedance amplifier followed by a voltage amplifier. Both schemes can achieve a gain of 2-4 M½ with around 8 -18 Mhz of bandwith. The circuits perform a square root signal compression in order to reduce the A/D converter dynamic range without decreasing the signal-to-noise ratio.
A front end amplifier for Silicon Drift Detectors (SDD) of the Alice Inner Tracking System at LHC has been designed in AMS 0.8um tecnology to meet the following requirements
To meet these requirements we have designed a transimpedance amplifier based on the configuration with active feedback principle recently developed in CERN; this circuit uses a cascode inverting amplifier as core amplifier, while the conventional feedback resistor is replaced by a MOS transistor biased in week inversion or in saturation via a simple current mirror. In this way it is possible to achieve 200-400 k½ of gain with a bandwith of 30 Mhz and a power consumption below 1 mW. A good performance to power consumption ratio is mandatory for the SDD readout because these detectors are very sensitive to temperature variations.
Due to the active element in the feedback loop, the circuit has two different modes of operation:
In both situations, the amplifier can easily accomodate the SDD leakage current. Moreover, when it works in the non linear mode the circuit performs a square root compression, that is useful to decrease the number of bits to be used for A/D conversion. We choose the second mode of operation. For the pourposes of the ALICE Inner Tracking System the 200-400 k½ gain is too low: to increase the gain without decreasing too much the bandwith a two stage configuration has to be used. One scheme we developed is a current amplifier followed by a transimpedance amplifier. For both stages the active feedback configuration can be used, because the amplifier can provide both voltage and current outputs. In this case it is necessary to compensate the first stage output DC current in order to avoid second stage saturation. The second stage has no compensation branch in order to decrease power consumption and the frequency compensation is carried out by a conventional feedback capacitor. In the other circuit we designed the active feedback amplifier works in the transimpedance mode and is followed by a voltage amplifier which provides both single ended and differential outputs. Both circuits have a peaking time of 20 ns, an expected rms input noise (at 1 pF of input capacitance) of 300 electrons and power consumption around 0.8mW/channel. Entensive test with a SDD detector are planned during the summer.
D.B. Kerwin, J.M. Benedetto, R.R.L. Sharman
UTMC Microelectronic Systems
4350 Centennial Blvd.
Colorado Springs, CO 80907
UTMC Microelectronic Systems has developed two radiation hardened process modules for hardening commercial CMOS processes and has demonstrated the effectiveness of these approaches at three different commercial foundries. UTMC Microelectronic Systems' Commercial RadHardTM technology using American Microsystems, Inc. (AMI) 0.6 micron commercial CMOS process achieves threshold voltage shifts of < 1 mV/krad(Si), with intra-device leakage well controlled to total dose levels exceeding 200 krad(Si). Inter-device leakage exceeds 150 krad(Si) requirements for UTMC Microelectronic Systems' 0.6 micron gate array family. UTMC Microelectronic Systems provides Commercial RadHard TM products that can be fully qualified (using MIL-STD-883, Method 1019) to a 100 krad(Si) radiation hardness assurance conformance level (RHACL), at a reasonable cost by using commercial CMOS processes.
Jim Swonger
Harris Semiconductor
Melbourne, Florida, USA 32902-0883
Signal processing electronics for front-end applications operates in difficult radiation environments, and hardened parts are required for reliable long-term operation. Hardened processes and parts have evolved over years of R & D and have been produced in prototype quantities. The large experiments now under development will increase the number of data channels by orders of magnitude, forcing manufacturing, procurement and assembly methods. Unless these improved methods are adopted, affordable systems will not be possible.
In this paper, we describe the use of Qualified Manufacturers List (QML) methodology to the production of hardened parts at Harris. The use of QML contrasts sharply with earlier procurement practices, most of which depended on rigorous controls over the manufacturer's procedures. It replaces these controls with the vendor's own commercial best practices allowing the specialized components to be built using the same facilities as commercial parts. With the strong reduction in demand for military parts in the US and other countries, this was a neccessary approach if qualified sources were to be available at all.
Renato TURCHETTA
LEPSI (CNRS/University)
23, rue du Loess
F-67037 Strasbourg Cedex
A CMOS mixed analog-digital circuit (APVD) for the silicon tracker in CMS has been designed in the radiation hard technology DMILL. This circuit is pin-to-pin compatible to the APV6, fabricated in a radiation hard process by Harris Semiconductor.
The APVD has been designed within a French-British collaboration of several laboratories: CEA-DAPNIA, IPN, IReS, LEPSI and RAL.
The design as well as the expected performances will be presented in this paper
F. Vasey, V. Arbet-Engels, G. Cervelli, K. Gill, R. Grabit,
C. Mommaert, G. Stefanini
CERN, Geneva (Switzerland)
We present the concepts underlying the development of a rad-hard optical link based on edge-emitting laser transmitters, single-mode optical fibre ribbons, multi-way MT connectors and pin-photodiode receivers operating at a wavelength of 1300nm. One-way transmitter- and receiver-building blocks, assembled using silicon waferboard technology, allow for high flexibility and modularity in the system design. This is illustrated by reviewing both the analogue-readout and digital-control optical systems of the CMS tracker, which are based on identical optoelectronic components. Ongoing developments and timescales to production are discussed.
The CMS experiment is planing on using large quantities of optical links for analogue and digital data readout as well as digital control and timing signal distribution. In particular, front-end links connecting pixel, tracker and calorimeter detectors to the front-end driver and controller modules will need to be radiation resistant, and thus deserve special developments. A radiation-hard optical link based on edge-emitting laser transmitters, single-mode optical fibre ribbons, multi-way MT connectors and pin-photodiode receivers is being developed. The wavelength of operation is 1300nm. Both laser- and pin-diode feature linearity and bandwidth characteristics suitable for analogue as well as high speed digital applications.
The strength of the optical system under development relies on the choice of a flexible assembling and pigtailing technology for the optoelectronic components: silicon waferboard technology. Both die and fibre are attached onto a common silicon submount and aligned to each other using passive or active techniques. The resulting sub-assembly is a low mass, small footprint (typ. 2x2x1mm), lens-free, epoxy-free (if required) transmitter or receiver module which qualifies to telecom standards.
A high degree of flexibility in the layout of the optical system can be achieved by using one-way sub-assemblies as basic building blocks. Single fibre links can be easily built using commercially available 1-way components based on silicon waferboard sub-assemblies, and multiway links can be realised by hybridising many 1-way sub-assemblies into one common package. Such a 4-way module is being custom developed for CMS. It can be (partly) populated with laser sub-assemblies, pin-photodiode sub-assemblies, or a mixture of both for bi-directional links. It is up to the designer to specify a configuration matching system requirements.
At production time, only known good sub-assemblies are packaged into the multiway module, thus significantly increasing the manufacturing yield.
The optical link is targeted at the CMS-tracker application, and most of the technological choices made during the development phase aim at fulfilling the tracker analogue-readout and digital-control system requirements. The architecture of the tracker optical readout system is shown in Fig. 1. At the front-end, the 4-way transmitters serve up to 1024 detector strips. Optical fibre ribbons originating from the transmitter hybrids are fanned-in after the second patch panel to 64-fibre cables running outside the tracker volume. Each cable connects 16 transmitter modules to one FED readout board. 3 patch panels are foreseen for ease of testing, installation and maintenance.
The CMS-tracker control system will make use of the same components, but used in bi-directional digital mode.
One-way sub-assemblies are being thoroughly tested for analogue and digital performance as well as radiation hardness and reliability, before the package development and system design work is complete. Progress is reported in the accompanying papers [1-4]
In order to start volume production in 1999 or early 2000, the bulk of the development work will have to be concluded by mid 1998 to allow for final prototype testing and write-up of the specifications. The currently ongoing industrial programme calls for delivery of the first 4-way packages in early 1998. The radiation hardness, reliability and performance tests performed on 1-way components in 1996 and 1997 will form the base on which the system functionality will be assessed. As both the chips and the coupling technology will be the same for 1-way and 4-way components, tests on 4-way custom modules will only need to confirm the results obtained on 1-way assemblies.
In parallel to internal qualification tests, prototype analogue links comprising laser driver, transmitter, receiver, transimpedance amplifier, fibre and optical connectors will be distributed to the CMS community for evaluation: 1-way links will be ready by mid 97, 4-way links by mid 98.
The investigated rad-hard optical link is based on edge-emitting semiconductor lasers as transmitters, pin-photodiodes as receivers and single-mode optical fibres and connectors. It sets a platform which could be common to all analogue and high speed digital links throughout CMS. It is very much in line with the current and emerging telecom standards and will thus benefit from technology improvements, multi-source component availability and cost reductions expected in the coming years. It allows to proceed via the safest route towards implementation of a functioning, radiation-hard and reliable optical link in a relatively short development time.
[1] K. Gill et al., "Radiation damage studies of opto-electronic
components for the CMS tracker optical links" submitted to this
workshop
[2] G. Cervelli et al., "Simulation and characterisation of the CMS
tracker optical readout chain" submitted to this workshop
[3] V. Arbet-Engels, "Characterization of optical data links for the
CMS experiment" submitted to this workshop
[4] P. Moreira, " An Integrated Laser Driver Array for Analogue Data
Transmission in the LHC Experiments" submitted to this workshop
A Weidberg
Optical links are being developed for the ATLAS SemiConductor Tracker. The links are based on radiation tolerant LED-fibre-PIN diodes. The links are used to transfer data off the detector and to receive all the trigger timing and control data required to operate the SCT modules. In order to minimise the number of links, the bunch crossing clock and the trigger and control data are multiplexed onto one fibre. Results on system tests are combined with irradiation data to verify the suitability of the system for 10 years operation at LHC. First results on the front end chips driver and demultipliexing chip are also presented.
The data transmission system for tracking detectors at the LHC will have to cope with very high data rates and a hostile radiation environment. The system will have to operate for many years with no or minimal maintenance which places severe requirements on the reliability of the system. Optical links are desirable for this application as they minimise problems of EMI and grounding and the represent fewer radiation lengths than electrical links. The optical links for the ATLAS SemiConductor Tracker are based on radiation tolerant LEDs-fibre-PIN diodes although VCSELS are also being considered as they could provide an attractive option for the higher radiation levels of the pixel detectors. Optical links are used to transfer the data off detector and to transmit the 40 MHz bunch crossing (BC) Timing signal, the first level Trigger and all the control data (TTC) to the SCT front end modules. To minimise the number of links the BC clock and the L1 and control data for an SCT module are multiplexed onto a single fibre. The data is encoded using a biphase mark scheme and is decoded on the opto-hybrids next to the SCT modules.
The elements of the system are described The on-detector opto-electronics consists of packages containing 2 LEDs and 1 PIN diode. The packages is made from silicon and is thus ideal for the application in that it is non-magnetic and that it represents a very small fraction of a radiation length. The results of signal to noise measurements of a prototype link are presented. These results are combined with the irradiation damage and lifetime measurements to understand the reliability of the system for 10 years of operation at LHC. Although these measurements indicate that the system will survive for 10 years, extra protection is added by employing immunity to single point failure; in the case of the optical links, this means that if one link fails that the data can be re-routed through a neighbouring link.
Two front end chips have been designed and fabricated for this system. The LED Driver Chip (LDC) drives the LEDs and the DORIC chip receives the TTC data and decodes the biphase mark data to provide the BC signal and the L1 and control data for the SCT modules. Results are presented on the performance of the LDC and DORIC chips as well as on their radiation tolerance.
P. Bailly(1), C. Beigbeder(2) , R. Bernier(2) , Zhang Bo(1), D.
Breton (2), G. Bonneaud(3),T. Caceres(2) , P. Cros(2), R. Chase(2),
J. Chauveau(1), L. DelBuono(1), F. Dohou(3), A. Ducorps (2), F.
Gastaldi(3), J.F. Genat(1), A. Hrisoho(2), P. Imbert(2), H.
Lebbolo(1), P.Matricon(3), C. Renard(3), L. Roos(1), G. Oxoby(4), S.
Sen(2), C. Thiebaux(3), K. Truong(2), G. Vasileiadis(3), M.
Verderi(3) , J. Va'avra(4), D. Warner(5), R.J. Wilson(5), G.
Wormser(2), F. Zomer(2)
(1) LPNHE, Univ. Paris 6 et 7, 75252 Paris Cedex France
(2) LAL Orsay, 91405 Orsay, France
(3) X-PHNE, Ecole Polytechnique, Route de Saclay, 91128 Palaiseau
Cedex France
(4) SLAC, Stanford University, PO 4349 Stanford CA94309, USA
(5) Colorado State University, Fort Collins, CO 80523 , USA
The DIRC front-end electronics chain for the BABAR experiment is presented. Its aim is to measure to better than 1 ns the arrival time of Cerenkov photoelectrons, detected in a 11,000 phototubes array and their amplitude spectra. It mainly comprises 64-channel boards (DFB) equipped with 8 ASIC VLSI full custom analog chips, performing zero-cross discrimination with 2 mV threshold and shaping, 4 ASIC VLSI full custom TDC chips, performing timing measurements with 500 ps binning and a readout logic selecting hits in the trigger window, and crate controller cards (DCC) serializing the data collected from up to 16 DFBs onto a 1.2 Gb/s optical link. Extensive test results of pre-production units will be presented.
Recent test results of the DIRC front-end electronics chain for the BABAR detector have been successfully completed. Its aim is to measure to better than 1 ns the arrival time of Cerenkov photoelectrons, detected in a 11,000 phototubes array and their amplitude spectra. It mainly comprises 64-channel boards (DFB) equipped with 8 ASIC VLSI full custom analog chips, performing zero-cross discrimination with 2 mV threshold and shaping, 4 ASIC VLSI full custom TDC chips performing timing measurements with 500 ps binning and a readout logic selecting hits in the trigger window, and crate controller cards (DCC) serializing the data collected from up to 16 DFBs onto a 1.2 Gb/s optical link. The analog chip time walk has been measured to be less than 1 ns, over an input range between 3 to 100 mV. The rms input noise is 150 uV and the cross-talk is at the per-cent level. The temperature time drift is 40 ps/deg. C.
The TDC chip has a differential linearity better than 50 ps. Its self-calibration feature makes its temperature drift negligibly small (10 ps /deg C). The DFB card treats incoming data with a 60 MHz clock and sends them back at 15 MHz. It allows complete tests of the chips through several calibrations procedures. On-board programmable FGPAs are extensively used for flexibility and easy commissionning. The DCC card receives commands and exchanges data with the DAQ using the Glink standard comprising Hewlett-Packard chips and Finisar optical interfaces that extract 60 MHz clocks from the serial transmission modulation and dispatch them to the DFB cards via a custom-made high-speed backplane. The clock jitter has been measured to be less than 60 ps during data transmission through the optical link. In summary, all measurements performed on the pre-production system tests have met or exceed design requirements. The design and review process of this electronics will also be presented with special emphasis on commonality and reliability issues.
Yasuo Arai
KEK, National High Energy Accelerator Research Organization
Institute of Particle and Nuclear Studies
yasuo.arai@kek.jp
and
Jorgen Christiansen
CERN, ECP/MIC
christia@sunvlsi.cern.ch
The architecture of a new integrated TDC has been studied for the ATLAS precision muon tracker. A data driven architecture using several levels of buffering have been chosen to obtain a flexible solution using the minimum amount of silicon area. Intensive simulation studies have been performed to verify its correct function under different working conditions. Matching of hits to triggers are based on time tags. Matched hits are read out on a shared 80 Mbits/s serial link. First series of prototype chips are planned for the end of 1997.
A highly integrated low-power TDC is required for the ATLAS precision muon tracker. A TDC in a CMOS technology can obtain a RMS resolution of ~250 ps using controlled delay elements as a part of a Delay Locked Loop (DLL) or a Phase Locked Loop (PLL). A Collaboration between CERN and KEK was started in 1996 for the implementation of a dedicated ATLAS muon TDC. Both groups have significant experience in the design of TDCs.
Intensive simulation studies have been performed with the Verilog simulator to optimize the TDC. A data driven architecture with a time tag based trigger matching function was found to give a very flexible TDC using the minimum amount of silicon area. To match the MDT granularity and minimize the total production costs the TDC will have 24 channels per chip. Simulations show that the chosen TDC architecture have a ~100% efficiency for hit rates up to 400 KHz per channel (Maximum expected rate = 130 kHz with a 5 times safety on background rates).
In addition to normal leading edge time measurements it is desirable to extract more information from the signal of the Monitored Drift Tube (MDT). The analog front-end can optionally generate the trailing edge from the last electron (constant latency from bunch crossing) or generate a pulse width proportional to the slew rate of the leading edge (for slewing correction). The TDC supports this kind of measurements by optionally pairing leading and trailing edge measurements into one combined measurement.
A data driven architecture using several levels of buffering was found to offer the required performance with a very high level of flexibility and minimum cost. Measurements are locally stored in each channel in a 4 words deep fifo before being merged into a common first level buffer. Triggers are on chip translated into trigger time tags and stored in a trigger fifo waiting to be processed. A time tag based trigger matching function takes care of extracting hits coming from a programmable time window after the trigger. Matched hits are passed to a readout fifo waiting to be read out on a 80 Mbits/s serial link shared by up to 16 TDC's controlled by a circulating token.
To be capable of integrating the required analog front-end electronics and the TDC on a printed circuit board located at the direct ends of the MDT tubes it is necessary to reduce noise and crosstalk to the absolute minimum. All digital signals to/from the TDC will use Low Voltage Differential Signaling (LVDS). Programming, monitoring, production testing and in system testing will be supported by using JTAG.
A complete behavioral model in Verilog is currently completed. This model will in the near future be extended into a register level model which will finally be mapped in to logic using logic synthesis. A first evaluation chip in a 0.7 um CMOS process is scheduled for the end of 1997. The final production version will be implemented in a 0.3 um CMOS gate-array technology.
M.Bercher, P.Busson, L.Faurlini, D. Lecouturier
The CMS level-1 trigger system will be able to retain interesting physics signal with good efficiency while rejecting background events from QCD. In order to achieve a high rejection power the electron/photon trigger algorithm involves both isolation cuts and longitudinal and transversal cluster shape analysis. The transversal cluster shape analysis is performed at the digital front-end level by a dedicated circuit working in pipe-line mode at 40 MHz. We report about the design of this circuit and the performances of a prototype already implemented in a field programmable gate array.
The electron/photon LVL1 trigger of CMS uses a 3x3 trigger cell sliding window processing. The electron/photon identification is based :
The lateral shower profile study is performed in the front-end electronics making use of the eta-profile of the transverse energy deposited in each trigger cell ( 6 eta-strips in the barrel; between 4 and 6 strips in the end-caps) as well as the computation of the total transverse energy in the trigger cell.
This transversal shower profile study results in a fine grain local isolation bit which is determined by the following peak-finding algorithm : -select the maximum ET sum of two adjacent eta-strips -compute R, the ratio between the maximum sum of two eta-strips and the total ET sum
-compare R with low and high programmable thresholds to get the LIL and LIH bits
-the final fine grain local isolation bit depends on the cell ET range
if ET < ET1 LI = 0
if ET1 < ET < ET2 LI = LIH
if ET > ET2 LI = LIL
where ET1 and ET2 are programmable thresholds.
Electrons and photons have R > 0.90 in 98% of the cases. The same criterium rejects the fraction of jets where two or more hadrons interact inside one trigger cell.
The high threshold (typically 0.95) is used in the definition of a low PT beauty electron trigger which requires a moderate efficiency and a high rejection power.
Introduction of this transversal shower profile study decreases the single electron/photon trigger rate by a factor ~ 2 with very high efficiency for the signal.
We discuss here the design of an ASIC ( TPG standing for Trigger Primitives Generator ) which will provide the LVL1 trigger system with the total transverse energy and the fine grain local isolation bit for each trigger cell of the ECAL ( ~ 4000 trigger cells in total for barrel and end-caps ).
Each TPG receives two trigger cells data sets, ie 12 10-bit numbers, at 40 MHz rate from the ECAL front-end digital electronics and generates the two trigger primitives for each trigger cell.
The two sets of trigger primitives are then combined in a single 16-bit word and a 5-bit Hamming code is appended to this word for further error detection by the LVL1 ECAL trigger system. The transfer of the resulting 21-bit frame to the LVL1 ECAL trigger system is performed by a 1 Gigabits/s optical link after synchronisation operations.
The heart of the TPG performs the computations of the total transverse energy and the fine grain local isolation bit for each trigger cell. This task requires 10 additions, 8 comparisons and 2 multiplications on 10-bit numbers as well as logical operations. We adopted a Top-Down methodology using a HDL description for the modelling of the whole TPG.
Prototyping of the TPG ASIC has already been done in a field programmable gate array from Altera ( Flex 50K ) using HDL synthesis tools. We will report on the performances obtained with this prototype and will discuss the design constraints for the final ASIC.
Ian Brawn, Alain Corre, Nick Ellis, Philippe Farthouat,
Georges Schuler
CERN
The ATLAS level-1 Central Trigger Processor (CTP) will correlate sub-triggerresults and form the global level-1 trigger decision. It will be implemented as a fully synchronous, 40 MHz pipeline processor. To evaluate the proposed CTP design, a demonstrator module has been built. This module implements all of the core functionality foreseen for the final system, but processes only one quarter of the data (32 input signals rather 128). Extensive use is made of FPGAs. The demonstrator has a latency of 2.5 bunch crossings. Presented here are the CTP demonstrator design, the software used to handle the demonstrator, and the results of beam tests with the demonstrator.
The ATLAS level-1 trigger has two distinct stages. In the first stage, sub-trigger processors work independantly and in parallel to parameterise events. In the second stage, the sub-trigger results are correlated by the Central Trigger Processor (CTP), which forms the global level-1 trigger decision. The proposed implementation of the CTP is a fully synchronous, 40 MHz pipeline processor.
The CTP receives a total of 128 bits of intput data. Typically, these bits indicate whether various energy and multiplicity conditions set by the sub-trigger processors have been satisfied. For example, one bit may flag the existance of at least 2 em clusters of energy greater than 20 GeV in anevent.
Data are received from the em cluster, jet, missing-ET, muon and hadron sub-trigger processors. Some inputs to the CTP are reserved for calibration triggers and special triggers such as cosmic ray events.
The inputs to the CTP are combined in coincidence, veto or 'don't care', to form 96 triggers (eg, one trigger could require at least 1 em cluster of energy >= 20 GeV, in coincidence with missing-ET >= 20 GeV). This process is performed using a look-up table. Individual triggers can then be masked, or prescaled to reduce the frequency of high-rate, less interesting triggers. The overall level-1 trigger decision (Level-1 Accept) is the OR of the 96 individual triggers. Deadtime vetos can be introduced to ensure a fixed deadtime after each positive Level-1 Accept, and to limit the number of accepts generated within a sliding window (eg, no more than 16 accepts generated within 16 microseconds). Monitoring and readout facilities are provided for the CTP.
In order to evaluate the proposed CTP design, a demonstrator module has been built. This module is a scaled-down version of the final system, processing only 32 input signals and forming 32 triggers. The demonstrator implements all of the functionality described above and, importantly, all of that functionality foreseen for the final system which lies on the critical time path. It thus provides a good indicator of the latency of the final CTP. The latency of the demonstrator is 2.5 bunch crossings.
As is proposed for the final CTP, the demonstrator implements its core logic in field-programmable devices (FPGAs and CPLDs). Most system parameters are stored in SRAM and can be reprogramed via simple VME access, without the need to reconfigure devices.
Software has been developed to test the CTP demonstrator and to provide a user-friendly way of controlling the many programmable parameters fo the module. This software is written in C, with a graphical user interface built using TCL/TK.
Stand-alone testing of the demonstrator shows it to be working as designed. In beam tests in July 1997, the CTP demonstrator will be run in conjunction with the level-1 calorimeter sub-trigger demonstrators. For the first time, it will be possible to test a complete level-1 processing chain, from the calorimeter output to the generation of the Level-1 Accept signal.
R.E. Breedon, H. Cooper, B. Holbrook, Winston Ko, P.
Murray, G. Song, C. Thanh
University of California, Davis, CA, USA
A switched capacitor array (SCA) will provide analogue storage for the cathode readout of the cathode strip chambers in the CMS endcap muon system. After a series of smaller prototypes, the first iteration of the full sized 16-channel, 96-cell per channel SCA is undergoing precision testing using a specially designed test board. As a result of several innovative design features, the chip exhibits a remarkably low level of cell-to-cell pedestal fluctuation. The system control and integration of the SCA, and test results including linearity, cross-talk, pedestal variation and other dynamic effects will be presented.
The first-level trigger decision is expected to be made available to the front-end electronics of sub-detectors in CMS after approximately 128 bunch crossings (3.2 us), during which time the signals must be held in temporary storage before being passed to the DAQ system or rejected. For the CMS endcap muon system, full-wave sampling and storage of the precise cathode measurement has been chosen for the higher level of control it allows over pileup effects (baseline shift) than other pipeline options. Our SCA design supports random addressing and simultaneous reading and writing for deadtimeless operation.
A pulse on a strip of a cathode strip chamber (CSC) emerges from the preamp/shaper (Tpeak = 100 ns) and is split into two signals: one for use in the level-1 trigger, the other sampled by the SCA at 20 MHz to preserve pulse height information for the precise position measurement. Seven or eight samples of each pulse saved in the SCA enable the precise cathode signal to be reconstructed to better than 1% accuracy, as required for track fitting and identification of pileup events. Sixteen cathode strip channels from each of the six layers in a muon station are connected to a front-end board (FEB) mounted on a chamber. Sixteen channels from one layer are handled by one SCA, so there are 6 SCA chips per FEB. Each channel has 96 capacitor cells; cells selected for readout are multiplexed within the SCA.
Writing to and reading from the SCA is directed by the Readout Controller (under development by Ohio State University) whose principle function is to generate write (every 50 ns) and read addresses for the cells of all the SCA channels on a FEB. To minimize noise, cell addresses are kept in a Gray code sequence. When a voltage is stored on a capacitor, its address is tagged so that it is taken out of circulation. The tag is reset when there is no local or global trigger associated with the address, the latency period is expired, or the stored voltage is digitized and stored in RAM.
The full sized SCA prototype ASIC was fabricated using the HP 1.2 um process via a submission to the MOSIS consortium. It has been tested to 12-bit precision using a test board designed and laid-out by an outside consultant. The test board provides the interface to the Tektronix Data Analysis System (DAS) 9200. The DAS selects test input voltages by programming the ADC on the test board, provides the SCA addresses, and passes the DAC output on for computer analysis. In preliminary testing, pedestal variation (rms) is less than 0.25 mV and non-linearity of selected cells is < 1%. Results from cross talk measurements and the characterization of dynamic effects will be presented. Improvements to the SCA design based onprototype testing and layout simulation will be discussed.
Jorgen Christiansen
CERN/ECP - MIC
1211 geneva 23
phone: +41 22 767 5824
Fax: +41 22 767 3394
Email: jorgen.christiansen@cern.ch
A 32 channel data driven Time to Digital Converter (TDC) has been implemented as an integrated circuit with an area of 34mm^2 in a 0.7um CMOS process. The time conversion is performed by storing the state of a Delay Locked Loop and a 16 bit counter. A two words deep de-randomizing buffer per channel is used before a common 256 hits deep level 1 buffer. Data from the l1 buffer are optionally matched to a trigger. Matching hits are stored in a 32 words deep read-out FIFO. At 40MHz the absolute RMS error of the TDC is 0.29ns.
Tracking detectors measuring the drift time of ionized tracks in an electrical field require a Time to Digital Converter (TDC). In the new generation of detectors (CMS, ATLAS, ALICE, LHC-B plus others) a very large number of TDC channels are required because of the large physical dimensions of the detectors and their high collision rates.
A data driven 32 channel TDC with on-chip first level buffering and logic to extract hits belonging to a trigger have been constructed. A data driven architecture significantly reduces the memory required for the first level buffer and is very flexible (programmable trigger latency and matching window). One common l1 buffer gives significant area savings but also introduces a potential bottleneck. This bottleneck has been relieved by a two hits deep de-randomizing FIFO per channel.
A programmable trigger matching function extracts hits belonging to a time window around a trigger, based on a comparison of the hit measurements to a trigger time tag. The trigger time tag is generated on-chip and temporarily stored in a 8 words deep FIFO to accommodate closely spaced triggers. Hits older than a programmed value are automatically removed from the l1 buffer when no triggers are waiting to be processed. Overflows of time counters are automatically taken care of and a special search mechanism is used to handle hits in the l1 buffer not being in perfect time order. Matched hits are passed to a 32 words deep read-out FIFO separated by event markers. Local event building is performed at the read-out using a circulating token.
Behavioural modelling (in Verilog) have been used extensively for architectural studies with large sets of different conditions. Different architectures have been evaluated from point of view of performance and minimization of logic and memory.
The TDC has been mapped into a 0.7um CMOS process from ES2 using 34mm^2. The Delay Locked Loop, the coarse counter and the individual channel buffers have been implemented in full custom. The rest of the chip have been implemented with standard cells and memory macro's.
The final version of the 32 channel TDC have now been verified with very good results. At 40MHz the absolute RMS resolution (including quantification, non linearities and noise) over its full dynamic range (16us) have been measured to be 0.29ns. Prototype chips have been found to work at frequencies up to 90MHz with a 0.17ns RMS resolution.
The 32 channel TDC is currently being evaluated for several future experiments (CMS muon detector, COMPASS, L3 cosmics upgrade, BABAR, etc.). A 64 channel VME module based on this TDC is now commercially available from CAEN. A similar data driven TDC is currently being designed for the muon detector of ATLAS.
A. Connors, J. Garvey, S. Hillier, D. Rees, R. Staley, P. Watkins,
A. Watson
School of Physics and Space Research, University of Birmingham, UK
E. Eisenhandler, M. Landon, J.M. Pentney
Queen Mary and Westfield College, University of London, UK
J. Edwards, C.N.P. Gee, A.R. Gillman, R. Hatley, T.P. Shah, V.J.
Perera
Rutherford Appleton Laboratory, UK
The core of the ATLAS level-1 calorimeter trigger system is the electromagnetic cluster-finding algorithm implemented in ASICs. The algorithm demands a high level of data fanout between modules containing the ASICs, which will be achieved by data transport at 160 Mbit/s across point-to-point transmission-line crate backplanes.
To prove the viability of this technique a small-scale backplane has been constructed, allowing data communication between nine cluster-processing modules in a demonstrator system installed at the ATLAS test-beam at CERN.
We present here some measurements of data crosstalk and bit-error rates.
The ATLAS experiment at CERN uses signals from ~3,600 electromagnetic and ~3,600 hadronic calorimeter trigger towers, each 0.1x0.1 in h-f space, to identify electromagnetic clusters, hadronic jets and missing transverse energy. For each trigger cell the ASIC-based electromagnetic cluster-finding algorithm searches inside a 2x2 window and also imposes isolation criteria inside a 4x4 window. The consequence of this is that data from every trigger cell is used in 16 copies of the algorithm as the window slides in 0.1x0.1 h-f steps. With fresh data arriving every 25 ns, and with 64 cluster-processing modules in the full trigger system, the sharing of data between different modules leads to a potentially severe bandwidth and I/O problem.
The proposed solution is to bring the core trigger cell data into the cluster-processing modules via front-panel connectors and to employ a point-to-point backplane in the rear-panel space to transport the shared data between modules in a serial format. Serialisation at 160 Mbit/s will allow data from each trigger tower to be transported using only two lines. As each cluster-processing ASIC will fully process 4x4 trigger cells, the algorithm will require data from a total of 98 trigger cells, so the number of ASIC input pads required will be only 196. In addition, this data rate leads to an acceptable minimum signal pin-count of 384 per backplane connector, assuming single-ended transmission.
In order to verify that such a backplane will operate satisfactorily, a scaled-down 3U-high prototype emulating the key features of the final design has been constructed and operated in the 36-channel trigger demonstrator system. It was designed to interconnect nine cluster processor modules, with each module transmitting/receiving data relating to four trigger cells to/from a maximum of eight other modules separated by up to 162.5 mm. Mechanically, the backplane is a 12-layer construction, with four signal planes, four ground planes and four power planes.
All signal traces are true striplines, with a characteristic impedance of 33 ohms and separated by grounded guard traces. Module connection is by means of 192-pin Metral connectors with a pin pitch of 2 mm, and with 52 ground connections distributed between the 84 signal pins. The cluster-processing modules themselves have matched-impedance traces and terminations, and the data are transported between them in NRZ format as 100K ECL signals.
The trigger demonstrator system will be evaluated in the ATLAS test-beam at CERN in July 1997, during which time preliminary measurements will be made of bit-error rates and inter-channel crosstalk with total backplane traffic approaching 35 Gbit/s. More detailed studies will follow in August 1997 when high-statistics measurements will be carried out in the laboratory.
Results and measurements from all these studies will be presented.
A. Connors, J. Garvey, S. Hillier, D. Rees, R. ;Staley, P.
Watkins, A. Watson
School of Physics and Space Research, University of Birmingham, UK
I. Brawn, N. Ellis, P. Farthouat, G. Schuler
CERN, Geneva, Switzerland
P. Hanke, E.E. Kluge, A. Mass, K. Meier, U. Pfeiffer, C.
Schumacher
Institut für Hochenergiephysik der Universität Heidelberg,
Heidelberg, Germany
E. Eisenhandler, M. Landon, J.M. Pentney
Queen Mary and Westfield College, University of London, UK
J. Edwards, C.N.P. Gee, A.R. Gillman, R. Hatley, T.P. Shah, V.J.
Perera
Rutherford Appleton Laboratory, UK
C. Bohm, M. Engström, S. Hellman, S-O. Holmgren, S.
Silverman, N. Yamdagni, X. Zhao
Physics Department, University of Stockholm , Stockholm, Sweden
The ATLAS level-1 calorimeter trigger system relies upon several key technologies which have been tested in a demonstrator programme. Operating with signals from prototype ATLAS calorimeters, the final phase of this programme has evaluated some critical aspects of high-speed data transmission, including 1.6 Gbaud electrical links and data fan-out on crate backplanes at 160 Mbit/s. Several trigger sub-systems have been interconnected for the first time to form a slice of the ATLAS level-1 trigger.
We present here some results from the operation of this demonstrator system in the ATLAS test-beam at CERN.
The level-1 calorimeter trigger system for the ATLAS experiment at CERN must identify isolated electromagnetic clusters, hadronic jets and missing transverse energy, using signals from ~7,200 electromagnetic and hadronic calorimeter trigger towers. A number of novel techniques and advanced technologies crucial to the proposed trigger architecture must be evaluated before design and fabrication of the full trigger system can commence. These studies have been pursued over the last few years in an extended programme of demonstrator projects, based around a 36-channel trigger system connected to a variety of prototype ATLAS calorimeters in a CERN test-beam.
Previous phases of the programme demonstrated ASIC implementations of pipelined algorithms (electromagnetic cluster-finding, bunch-crossing identification for slow pulses, etc.) and their operation in a test-beam environment. The final major phase described here concentrates on the problems of data transport at different stages of the trigger processing chain, and interfacing to other trigger demonstrator sub-systems to form a complete level-1 calorimeter trigger slice.
In the final ATLAS trigger system, the trigger data will be transported off the calorimeters in analogue format and digitised to 10-bit precision in a front-end sub-system local to the trigger processing electronics. The total digital bandwidth out of the front-end system will approach 300 Gbyte/s, so several different technologies have been evaluated for the links to the processors. One approach which has been studied achieves four data channels per link using the Hewlett Packard G-link chipset running at 1.6 Gbaud, and a variant of this technique using a Multi-Chip Module (MCM) implementation has also been evaluated. Another solution which has been explored is a simple low-cost link technology using discrete high-speed logic.
The ASICs which will perform the electromagnetic cluster-finding algorithm in ATLAS each have an input bandwidth of ~32 Gbit/s, so to retain an acceptable pin-count they will receive their input data in a serial/parallel format at 160 Mbit/s. The high-level data fan-out between ASICs located on different trigger processing modules (as demanded by the cluster-finding algorithm) will be achieved by a point&endash;to&endash;point transmission-line crate backplane operating single-ended at 160 Mbit/s. All these aspects of data transmission and reception at 160 Mbit/s, in a form closely emulating the final ATLAS trigger system, have been studied in the demonstrator programme. The ATLAS trigger requirement of data capture "on the fly" for recording as a monitor of trigger performance has also been evaluated, using front-end demonstrator modules.
An important goal for this final phase of the demonstrator programme is to establish interfaces between the digitisation system, the electromagnetic cluster-finding system, the front-end modules, the jet processing demonstrator system and the prototype Central Trigger Processor, thereby forming a "slice" through the level-1 trigger for the first time. Test-beam results will be presented from the operation of the full system connected to a prototype ATLAS calorimeter.
J. Ero, T. Ladzinski, N. Lejeune
CERN Div. ECP
The Dual PCI Input-Output Processor is a board developed for the CMS DAQ. The i960RP type embedded processor has direct access to two separate PCI buses, can act as bridge between them. The board can be inserted between the CMS-RDPM and the link controller interface boards. It establishes a fast control of the Link Interfaces increasing the readout speed. It gives a possibility to perform check tasks and certain level of data compression. Equipped with an RT Operating System it becomes the kernel of a simple local Data Acquisition System, which has an application field at the beam tests.
The CMS Data Acquisition System's Readout Dual Port Memory (RDPM) uses a PCI Mezzanine Connection (PMC) for forwarding the output data blocks towards the Link Interface (ATM, Fibre Channel, etc.)Cards. The control of these cards happens through the VME control interface for the setup-like procedure and done by the RDPM's internal list processor for the data-block-level control. When putting a dedicated I/O processor in between the RDPM output and the Link Interface cards it is possible to perform all control tasks by this processor. The processor has multiple PCI connections, which allows to control two Link Interfaces with doubled link bandwidth. The processor's own computing power makes it possible to perform simple data correction or data compressing tasks. Porting a Real-Time Operating System on the processor and mounting mass-storage peripherals instead of Link Interface makes it possible to build a miniature Data Acquisition System.
The processor chosen for application on the I/O processor board is the Intel's i960RP. The processor's core is a i960JF unit. The chip contains two fully equipped PCI bus connections with a dedicated bridge circuit between them. The third bus interface connects to a local bus. There are bridge circuits between the local bus and both PCI buses too. A sophisticated memory controller allows to connect SRAMs and DRAMs to the local bus directly without any glue logic. On-chip DMA controllers transfer max. 2kByte data blocks between the local bus and any of the PCI buses with full 33 MHz transfer speed.
The I/O processor board is a full size PCI card. The processor's primary PCI interface is connected to the PCI connector directly. The card contains 512kByte SRAM, 2MByte fast synchronous Flash memory and a socket for max. 16MByte DRAM. It is equipped with serial and parallel interfaces. The secondary PCI bus is built in form of two PCI Mezzanine Card (PMC) slots. The processor fully controls the secondary PCI bus and can become master and slave on the primary bus.
The size and speed of the Flash memory allow to store all basic programs there. It contains the processor's setup tables, the start-up programs, a basic monitoring program which performs board specific tasks, like programming the Flash and perform fast configuration on PMC boards. The Flash also contains a version of Mon960, Intel's monitor program for i960 processors and the runtime module of VxWorks operating system. The full operating system, being a cross development system runs on a workstation, while the download of the test programs is done using the primary PCI bus or the serial connection.
Several tests were performed with the I/O processor board in order to measure PCI configuration features, transfer rates, interrupt response behaviour and efficiency of different readout sequences. All these prove that the I/O processor represents a powerful tool for data readout and forwarding.
The next version of the I/O processor will be built in VME format with direct connection to the RDPM board's output PMC connector. This forms a small VME-format equipment, which can be extended by PMC SCSI controllers and network interface making up a small, downsized Data Acquisition System. Such system can have an application field at test beam experiments and in test benches for studying Event Builder structures.
D. Francis
A prototyping effort for a small scale yet fully functional vertical slice of the ATLAS DAQ system is ongoing since early 1996. The Read-Out crate is the modular element sitting between detector front-end electronics and the event builder. The current architecture and organisation of the Read-Out crate is presented. A prototype implementation of the Read-Out crate based on technology embedded in VME is described. The performance assessment, based on a detailed series of measurements, of the current protoype implementation will be discussed.
The final design of the Data Acquisition (DAQ) and Event Filter (EF) system for the ATLAS experiment at the LHC is scheduled to start not earlier than 1999. Clear specification of the detector requirements, further technology investigation of hardware and software elements and integration studies are still required to reach maturity for the design. The ATLAS DAQ Group has chosen to approach such pre-design investigations via a structured prototype, supporting the evaluation of hardware and software technologies as well as their system integration aspects. A project has been proposed and approved by the ATLAS Collaboration for the design and implementation of a full DAQ/EF prototype, based on the Trigger/DAQ architecture described in the ATLAS Technical Proposal and supporting studies of the full system functionality, although obviously not the required final performance. For this reason, it is refered to as ATLAS DAQ Prototype "-1". The prototype consists of a full "vertical" slice of the ATLAS DAQ/EF architecture, including all the hardware and software elements of the data flow, its control and monitoring as well as all the elements of a complete DAQ system, from the detectors Read Out Driver to data recording.
This paper focusses on the Read-Out crate (ROC) element. This is the modular element which sits between the detector electronics and the event builder.
The current design of the ROC is based on an architecture which individuates functions and associates them to either isolated or interacting modules: 1) Detector read-out, buffering and data distribution to other elements in the crate. This function is provided by the read-out buffer (ROB) module. 2) The control of the flow of data within the crate, in collabotion with the trigger sub-system. This functionos performed by the trigger (TRG) module. 3) The merging of fragments of accepted events from the ROB memories into a ROC-wide fragment. This fragment is then passed to the event builder to be included in the full event. This function is provided by the event filter interface (EFIF) module. 4) Other ancillary functions needed locally in the crate: the control of the ROC, the handling of errors and the support for event monitoring. The local DAQ (LDAQ) is the component implementing these ancillary tasks. 5) Intra-crate links and related communications protocols to support the variuos data communication functions.
A fully functional prototype of the above has been implemented based on VME modules. It uses PowerPC based single board computers running mainly the LynxOS operating system. PCI is used as the I/O bus within a module to connect to external links via interfaces based on the PMC standard. VME is used as the physical intra-crate bus on which several communication protocols run. The integration of commodity hardware and software is also part of this prototype ROC.
The prototype ROC has been used to perform a detailed set of measurements of various elementary and combined functions of the ROC. These measurements provide the performance assessment of the current ROC prototype and are used to extrapolate performance to e.g. different technologies.
A Fucci
CERN/ECP
High speed data buffering is required at different levels in the readout chain of LHC experiments. The basic data acquisition unit for all sub-detector readout systems is expected to be a programmable, message-driven, multi-port memory (DPM) with high throughput (>100 MB/s) and high capacity (>100 MBytes). Moreover, during the present phase of design and evaluation of readout components, dual port memories are the basic test tools to generate and acquire data to/from a high speed digital system such as a front-end readout or event builder switch. CMS is developing a series of DPM modules for applications ranging from testing, in realistic LHC conditions, the event building architecture to final data acquisition systems.
Diminique GIGI
CERN ECP-CMD
All the present RDPM prototypes are implemented in 6U-VME boards. They contain all the necessary control logic for two independent PCI busses.
The VME bus is also used as the readout bus, hence the RDPM has a programmable VME-DMA controller, capable of multiDMA sparse readout at about 60 MB/s.
The logic implementation uses FPGA circuits of XILINX or ALTERA technology.
The dual port memory module is a PMC-PCI board of either 8MB static or 32 MB dynamic RAM, and about 400 MB/s bandwidth.
The output PCI bus is build around a list processor engine that should be able to drive ATM , FB and other PMC-PCI link protocols Four prototype boards are currently in use in various test environment including links to personal workstations.
Rob Halsall
Rutherford Appleton Laboratory
The CMS tracker Front End Driver (FED) prototype is a technology demonstrator which when fully configured is capable of receiving, digitising & processing the data from 64 optical fibres carrying the analogue data frames from 128 front end chips. At this density of optical channels around 700 FEDs occupying 50 Crates will be required in the counting house to process the data from 12 million detector channels in the CMS micro strip tracker.
The prototype, implemented as a 9U by 400mm VIPA compatible VME bus module, receives 64 of these optical signals, converts them to electrical levels and then digitises with 64, 10 Bit at 40 MHz, Analogue to Digital Converters (ADCs). This is then followed by Field Programmable Gate Array (FPGA) based Digital Signal Processing (DSP) which at 100 kHz First Level Trigger (FLT) rate extracts around 50 M bytes/s per percentage occupancy of hit data from the 1.6 G byte/s of digitised analogue data streams input to each FED.
The module has been designed in a flexible manner with major functions implemented as plug on mezzanine cards. Flexibility is further enhanced by the use of high gate count in-circuit re-configurable FPGA components for processing. In particular the post ADC DSP, implemented in FPGA allows for investigation of re-ordering, common mode removal, pedestal removal, noisy channel suppression & hit & cluster finding algorithms on the data stream.
To compliment this flexibility a full set of software drivers is provided either as a C library or labview modules. These software drivers isolate the user from the complexities of the highly programmable hardware minimising the users code development. Changes to the programmable hardware can be made transparently to the user via a software upgrade to the libraries and FPGA configuration files distributed via ftp server.
To date eight tracker FED prototypes have been produced and these are in use at Imperial College, Brunel & CERN. Following on from the successful use of the FED prototype module in the September 96 beam tests at CERN the development program continues this year with the integration of the FED with the opto, TTC & DAQ systems. The ultimate aim is to produce a demonstration of a full readout chain by the end of the year.
This paper will discuss the design of the prototype FED and look at all aspects of the development program presenting results of performance tests where appropriate.
The FERMI Collaboration
Presented by Magnus Hansen, CERN/ECP
The activity in the FERMI collaboration has during the last two years been concentrated on providing architectures that fulfill the requirements set by the interested experiments in the domain of calorimeter readout. Currently, FERMI is being implemented on all calorimetric detectors in CMS, and is the baseline for the ATLAS Tiles calorimeter prototype.
As a consequence, new digital ASICs are being developed in line with the final requirements, including optimisation and simplification of almost all functional units.
The current status of the project is described, together with the most recent performance results from beam tests on different calorimeter prototypes. Excellent results, both in terms of energy resolution and trigger feature extraction performance, fulfilling the requirements of the detectors, are provided.
The activity of the FERMI project has during the last two years concentrated on providing architectures that fulfil the requirements set by the interested experiments in the domain of calorimeter readout. Currently, FERMI is being implemented on all calorimetric detectors in CMS, is the baseline for the ATLAS Tiles calorimeter prototype. We describe the current status of the project, and the most recent performance results from beam tests.
As a result of the industrial progress, now providing ADCs with up to 12 bits resolution at 40 MHz, the analog developments have been restricted to the compressor function. A detailed theoretical analysis of bandwidth and slew rate requirements for LHC applications have been done and a new version of the compressor has been designed and submitted to foundry.
An improved and more complete version of the Channel ASIC has been produced in the AMS 0.8 micron technology, and is currently under evaluation. In the final implementation, the functionality of the current Channel ASIC will be split into two parts in order to provide full flexibility to linearise the digital data after any analog dynamic range compression scheme.
The service functions have been split into individual ASICs, i.e. the level 1 filter ASIC, containing the feature extraction for the first level trigger, the final readout filter ASIC, which provides the DAQ system with a single value extracted from the time frame representing the full pulse, a Read-Out Controller, responsible of the control and of the transfer of the data out of the Multi-Chip-Module and, finally, the Clock Manager which controls and distributes the internal clocks.
The fault tolerance strategies, i.e. redundancy, reconfigurability, concurrent processing and coding for error detection and correction have been implemented into the design of the digital ASICs.
Multi-Chip-Module (MCM) substrates have been fabricated, both as technology test vehicles and as FERMI prototypes. Results show that the technology is fully understood and a fully functional MCM is currently under test.
The irradiation program with gamma, neutron, protons and heavy ion sources, including thermal cycling of the irradiated samples, is continuing. Both FERMI developed ASICs and commercial components have been irradiated. Detailed results have been obtained on error rates and mechanisms on these items.
Beam tests on different calorimeter prototypes have been carried out and provide excellent results in terms of both energy resolution and trigger feature extraction. Further tests are in preparation together with the ATLAS and CMS Collaborations.
The project is now in the phase of finalising solutions fulfilling the requirements set by the LHC experiments.
R.Halsall, W.J. Haynes et al
Rutherford Appleton Laboratory, UK
The CMS detector at LHC will contain over 12 million electronic channels, with most assigned to silicon and MSGC tracker devices. On-detector ASICs will be read out into the Data Acquisition System (DAQ) via Front-End Driver (FED) receiver electronics.
This paper will discuss the evolution of the tracker Front End Driver for CMS with consideration of a common FED base module approach for all subdetectors. Such a FED might be based on a standard (VIPA) 9U by 400mm base module with up to 8 slots for PCI Mezzanine Cards (PMCs). Detector-dependent PMCs would be used to customise the FED for a specific subdetector with the base module providing all the common DAQ services such as Timing, Trigger and Control (TTC) with fast data links to the DAQ and Computer infrastructure.
The FED base module represents a common, collaborative, development primarily led by the requirements of the tracker system in the first phases. The other subdetector groups are, in principle, left to develop just the detector-dependent PMCs. Ultimately there is the possibility of only two types of detector-dependent PMC, namely analogue (Silicon, MSGC and Pixel) and digital for sub detectors such as the calorimeter which digitise at the front end. The strategy of a common FED base module should not only bring the advantage of standardisation but also the benefits of reduced software development and ease of maintenance over the long lifetime of LHC.
The next stage in the CMS tracker program is the development of a detector dependent ADC PMC prototype which will be available in the first quarter of 1998. This will initially be used on commercial 6U VMEbus single board microprocessor platforms but could also be readily integrated into Personal Computers with a PCI-PMC adaptor.
Much can be put into context by drawing upon the experiences already gained in implementing PMC designs in other particle physics applications. In this respect, this paper will also discuss the PMCs already developed or under consideration for the readout of the silicon trackers in the H1 and MINOS systems.
Presented by Greg Heath, University of Bristol, UK.
The design of the Level 1 calorimeter trigger system for CMS will bepresented. CMS plans to trigger mainly on electron and photoncandidates, jets and missing transverse energy, and combinations ofthese, as well as muon chamber signals. The calorimeter triggerprocessing takes place in three stages: primitive extraction, featurerecognition and feature sorting. All processing is performed in fullysynchronous, deadtimeless pipelines clocked at the LHC frequency of 40MHz, or multiples thereof. The status of design and prototyping work forall stages of the processing will be reviewed. The development of afast, pipelined sort algorithm for the later stages of the processingwill be described.
The Level 1 trigger for CMS will be based on combinations of signals forhigh transverse momentum leptons, photons and jets. Apart from theidentification of muon tracks, all of these signals will be derived frominformation provided by the CMS calorimeters. In this paper I willdiscuss the requirements on the calorimeter trigger processing, asdetermined by simulation studies. I will then review the design statusof the various elements of the processing pipeline.
The central CMS calorimetry will be performed by a homogeneous crystalelectromagnetic calorimeter (ECAL) and a sampling hadronic section(HCAL). The ECAL consists of 110000 crystals of lead tungstate (PbWO4).The HCAL is a Cu/scintillator device with projective towers of size0.087 in pseudorapidity eta and azimuthal angle phi. ECAL and HCAL bothsit inside the main solenoid of CMS which provides a uniform 4T magneticfield, and cover eta values out to plus/minus 3.0. They are complementedat small angles by the Cu/quartz fibre very forward calorimeter VFCAL,which extends the eta coverage to plus/minus 5.0. The trigger processingsearches for electron/photon candidates and jets in the centralcalorimeters, and forms sums of total and missing transverse energy overthe whole eta range.
Simulation studies of various trigger requirements have been used todetermine both the acceptance for physics channels of interest, and thetrigger rate due to the background of standard QCD processes. Physicschannels studied include the production of Higgs bosons and SUSYparticles, b hadron production and semileptonic decay at low LHCluminosity, and inclusive leptonic decay of W bosons. These studies showthat a combination of triggers on single and multiple leptons and jets,with differnet transverse energy thresholds, can give good physicscoverage and acceptably low trigger rates. They also show the importanceof powerful electron/photon pattern recognition to discriminate againstmisidentified jet activity.
The trigger processing in the central eta region will be based oninformation from ECAL and HCAL trigger towers. The geometry is such thatthe towers match up in the two detectors. The trigger towers in the HCALare simply the projective towers used in the readout. However in theECAL, each tower covers 36 crystals in the barrel region eta<1.5, and10--25 crystals in the endcap regions. The first stage of triggerprocessing will be located close to the readout pipelines for thecalorimeters, and will extract primitive information for each triggertower. In the HCAL this will simply be the transverse energy recorded ineach trigger tower. In the ECAL, however, use will be made of the veryfine granularity of the detector to produce local isolation informationfor use in the electron/photon algorithm.
The next stage of processing will take place in 18 regional triggercrates, with each crate covering a region equivalent to half the etacoverage of the calorimetry by 0.35 (20 degrees) in phi. Electron/photoncandidates and jet activity will be searched for in 8 regions of 4x4trigger towers, or 0.35x0.35 in eta and phi in each crate, covering thewhole eta range of the central calorimeters. For each electron/photoncandidate, the transverse energy and degree of isolation are passed onto the subsequent processing, along with the jet transverse energy inthe region. In addition, the regional crates form sums of transverseenergy and its components for all trigger towers and including the VFCALcontribution.
The final processing step produces overall sums of total and missingtransverse energy, and identifies the most energetic electron/photon andjet candidates, for use in the overall CMS Level 1 trigger decision.Provision is made to send up to four candidates in each of theelectron/photon and jet streams. We plan to provide two electron/photonstreams, to allow isolated and non-isolated candidates to be treatedseparately.
Most of the critical components of the trigger system, including ASICsand backplane interconnect technology, are now being prototyped. Some ofthese developments will be described in detail in other contributions tothe conference. I will discuss work in other areas, in particular thedevelopment of a fast, pipelined sort algorithm for use in the finalstage of the processing.
Tomasz Ladzinski, Dirk Samyn
CERN - ECP/CMD
The proposed CMS data acquisition system will be built around a central switching unit. A methodical study of data links and event building performance is therefore a crucial point in the development of the readout system. A modular OO software environment for testing CMS DAQ prototypes is presented. Results of point to point link tests of various technologies obtained in test setup environment are further shown. A short overview of event building aspects is given, together with a more detailed description of test bed assembled out of custom (CMS-RDPM) and commercial(Fibre Channel/ATM) products. The most recent results from the ongoing activities in the field of event building will be presented.
The CMS data acquisition system will be based around a central switching unit. It is expected that a commercial switch as well as standard data link technologies will be chosen for event building. These off-the-shelf products will be integrated with custom made hardware, built to suit the needs of the detector. In this paper we present the developments that have been done in CMS in order to build an event builder demonstrator, combining both the state-of-the-art networking products and current CMS Readout Dual Port Memories hardware.
In order to test such a system, a considerable amount of dedicated software must be written. We present a modular object oriented software environment that was developed to test the various components as well as the entire prototype system. By using object technology we have been able to produce class libraries used in an operating system environment of a workstation and in a standalone VME based PPC processor module running no operating system at all.
A number of data link libraries were developed and we present the results for point to point evaluation tests of some commercial interfaces of two technologies: ATM and Fibre Channel - all network adapters being PCI and/or PMC compliant.
The same class libraries are further on used in analysis of switched connections. As of today the latency of Fibre Channel switches in class-3 mode is of the order of tens of microseconds. Therefore we have focused our attention to comparison of event building strategies based on two different technologies: Fibre Channel class-1 circuit switching and ATM packet switching. With the first technology, the considerable overhead of connection setup implies the introduction of superevents to event building. Consequently the RDPM settings in the two technologies cannot be identical. However, our test bed is designed in such a way as to allow maximum flexibility. Due to limited number of resources our demonstrator system started with a 2x2 size. It comprises CMS developed Readout Dual Port Memories, PMC data link adapter boards, switch, PCI data link adapter boards and workstations. Scheduling of events to SFI emulators in the readout network is performed by an event manager unit running on a VME PPC module; the command network being VME.
The most recent results regarding bandwidth as well as latency issues from the ongoing activities around the event building will be presented at the workshop.
corresponding author Paolo Morettini
We present second level trigger for the ATLAS experiment based on the pixel vertex detector. This trigger is designed to tag individualb-jets on the basis of the presence of tracks having large impact parameters to the primary vertex. Moreover, it can allow the detectionof secondary vertexes and the evaluation of their invariant mass.
The tagging of b-jets and the selection of specific b decay modes are important issues for the trigger of LHC general purpose experiments, where the high b production rates do not allow the storage on tape of all beauty events.
Traditional b-trigger strategies are based on the detection of high p_tleptons, hadrons or jets. We present here the design of a second level trigger for the ATLAS detector, which selects beauty through its lifetime. This trigger is based on the use of the three layer silicon pixel vertexdetector. Thanks to the high granularity, the low average occupancy and the proximity to the primary vertex the pixel detector alone can quicklyreconstruct the tracks inside a jet "region of interest" defined at the first trigger level, compute their impact parameter to the primary vertex and perform a jet-based b tagging. Also, it can allow the reconstruction of secondary vertexes inside the jet and the computation of their invariant masses, providing an effective way to select specific b decay modes of interest. We will show how the performances we can achievecan improve the trigger acceptance for several interesting channels, such as B -> pi pi or H -> bbbb, at various luminosities.
We illustrate how the reconstruction algorithms have been optimized in order to achieve a good trade-off between physics performances and computing efficiency. From the architectural point of view, we illustrate advantages and disadvantages of two possible schemes: a centralized scheme, where all the data are transferred to a trigger farm, and a localized scheme, where every section of the detector performs locally, at the level of the read-out buffers, most of the processing.
M. Mota
LIP, Lisboa / CERN, Geneva
J. Christiansen
CERN, Geneva
A 4 channel, self-calibrating, High Resolution Time to Digital Converter with an RMS error below 49 ps over a dynamic range of 3.2 us has been developed. Its architecture is based on an array of delay locked loops and a 8 bit coarse time counter driven by a 80 MHz reference clock. Time measurements are buffered in two time registers per channel followed by a common 32 words deep read-out FIFO. The HRTDC has been built in a 0.7 um CMOS process using 21.6 mm^2 of silicon area.
High precision tracking detectors and Time Of Flight (TOF) detectors often need to perform high resolution time measurements on a very large number of detector channels. The required time resolution and accuracy for this kind of applications is in the range of 10 - 100 ps over a limited dynamic range.
Extended dynamic ranges are, though, often required at a system level to obtain time tagging of events for off-line analysis. Traditional time to amplitude TDC's can obtain very high resolution but suffer from low integration levels and short dynamic ranges. They are also known for being very sensitive to changes in temperature and supply voltage and have relatively large non linearities compared to their resolution.
A High Resolution TDC (HRTDC) was developed in order to serve the needs of detectors such as the ALICE's PesTOF counter. This detector requires precise time measurements on ~ 380,000 channels in a highly integrated environment. Using an Array of phase shifted Delay Locked Loops (DLL) it is possible to obtain a very fine interpolation within a period of a reference clock. Dynamic range expansion is easily achieved by counting clock cycles. Two counters using opposite phases of the clock are used to make this expansion unambiguous. This kind of TDC can obtain very good linearity and time resolution using a standard CMOS technology. Other advantages of this technique are the absence of dead time between measurements and self calibration using the clock as the time reference for the DLL array.
The DLL array using time differences between different delay paths is very sensitive to systematic and random variations in these paths. A considerable design effort has been spent to optimize matching and reduce noise coupling in the delay elements and the phase detectors in the DLL's. Differential input receivers have been implemented for the reference clock and the four channels to ensure good immunity to external common mode noise .
When a channel is hit, the state of the DLL array and the two phase shifted coarse time counters are latched in a 2 words deep channel buffer, before being merged into a common data path were the information is suitably coded and the correct coarse time count is selected. Finally the measurements are stored in a 32 words deep FIFO before being read out. This architecture, with a smaller channel FIFO and a large common read-out FIFO gives the best compromise between good double pulse acceptance and small silicon area.
A prototype TDC has been built in a standard 0.7um CMOS technology using 21.6mm^2 silicon area. The DLL array and the 4 channels with their two words deep FIFO has been implemented in full custom and the rest of the chip uses standard cells and a memory macro. The differential and integral non linearities of the TDC have been measured to 34 ps and 39 ps ( RMS ) respectively using a statistical code density test with a 80 MHz reference clock. This kind of measurement excludes the quantization error and all error sources of random nature ( noise ). The overall time resolution of the TDC ( including these error sources ) has been measured to 49 ps using a computer controlled passive coaxial phase shifter.
D Myers
CERN/ECP
Whilst in the past a certain amount of duplication took place between experiments the reduction in funding and staff will impose improved use of resources for LHC. In particular, it can be argued that there are no technical reasons why the four experiments need to have independently-developed control systems. However, if care is not taken one can end up with incompatible control systems for each sub-detector within a single experiment. This paper considers the issues which must be tackled in order to avoid such a Tower of Babel.
C.Bacci, F.Ceradini, G.Ciapetti, F.Lacava, A. Nisati,
Petrolo, L.Pontecorvo, S.Veneziano, L.Zanello
INFN Sezione di Roma,
Universita' di Roma La Sapienza and Universita' di Roma3, Rome Italy
R.Cardarelli, A. Di Ciaccio, R.Santonico
INFN Sezione di Roma2,
Universita' di Roma Torvergata, Rome Italy
We present the design and implementation of the first level muon trigger in the barrel region of ATLAS. The trigger is based on the use of a dedicated fast, finely segmented gaseous strip detector (RPC), Resistive Plate Chamber, to unambiguously identify the interaction bunch crossing and to provide a sharp threshold over a large interval of transverse momentum. The transverse momentum selection is done with a fast coincidence between strips on different planes, whose number is defined by the need to minimize the rate of accidental coincidences. The different momentum selection criteria required by the relevant physics processes, are met using low-pT and high- pT trigger. The trigger logic is done with a coincidence matrix circuit, based on a dedicated ASIC.
The first level muon trigger of ATLAS in the barrel region, is based on fast finely segmented detectors, to identify penetrating charged particles, pointing to the interaction region. The trigger is designed to unambiguously identify the interaction bunch crossing and to provide a sharp threshold over a large interval of transverse momentum. For the muon trigger system in the central toroid, Resistive Plate Chambers (RPC) are proposed for their good time resolution, easiness in the segmentation and low cost of production.
The transverse momentum selection is done with a fast coincidence between strips on different planes. The number of trigger planes is defined by the need to minimize the rate of accidental coincidences and to optimize the efficiency. To reduce the accidental rates to a level lower than the prompt muon rate, the trigger will operate in two projections, r - z and r - f. Thus the trigger detector will also be used to provide the coordinate in the non-bending plane( r - f) to the muon tracking system. The different momentum selection criteria required by the relevant physics processes are best met using a low-pT and a high-pT trigger.
The trigger scheme uses three stations, two middle stations (MB), each made of two RPC planes and the outer station (BO), made of two RPC planes. The low-pT trigger requires a three fold majority of the four middle planes, while the high-pT trigger requires a coincidence of the two outer planes with the low-pT trigger .
The trigger logic is done with a dedicated coincidence matrix circuit. The i - j inputs to the coincidence matrix, are given by the signals from the different planes. The transverse momentum threshold is defined by a "road" in the matrix and a trigger signal is generated when there is a valid coincidence within the road. The size of the matrix is 32x48 and the circuit will operate with three different thresholds simultaneously.
The time resolution of the trigger system should be smaller than the bunch crossing period of 25 nsec. A x4 time interpolator (160 MHz) is used to tag the bunch crossing.
The coincidence matrices will be distributed along the apparatus on boards each containing one matrix. The information of four coincidence matrices will be elaborated by a PAD board. Both coincidence matrix and PAD boards are attached to the trigger detector. The smallest Region-of-Interest (ROI) defined by the trigger system is DhxDf ~0.1x0.1.
The trigger system is segmented into 32x2 (h > 0 and h < 0) F sectors. The information of 7x2 (low-pT and high-pT triggers )h PAD's will be collected by the Sector Trigger Logic and the outputs of the sector triggers will be sent, via optical links, to the Central Muon Trigger processor that generates the global muon trigger information that is passed to the Level-1 Central Trigger Processor. The total level-1 muon trigger latency is less than 2 msec.
The information for the read-out of the trigger strips is collected by 16 Read-Out-Drivers (ROD's), located around the detector and is sent to the Level-2 trigger and read-out system.
I. Brawn, A. Connors, J. Garvey, S. Hillier, D. Rees, R. Staley,
A. Watson
University of Birmingham, UK
C. Geweniger, P. Hanke, E. Kluge, A. Mass, K. Meier, U.
Pfeiffer, A. Putzer, K. Schmitt, C. Schumacher, K. Tittel, M.
Wunsch
Institut für Hochenergiephysik der Universität Heidelberg
E. Eisenhandler, M. Landon, J.M. Pentney
Queen Mary and Westfield College, University of London, UK
J. Edwards, C.N.P. Gee, A.R. Gillman, R. Hatley, J.L. Leake, G.C.
Lewis, T.P. Shah, V.J. Perera
Rutherford Appleton Laboratory, UK
This paper describes the design and the programming of a Front-End Module (FEM) for the first-level trigger, which is part of a demonstrator program to test and harden design techniques applied to high-speed data transmissions, Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs). The programming of the module is one step closer to the final ATLAS trigger system where calorimeter trigger tower data from a bunch crossing that generates a level-1 accept signal must be captured at run time for recording. We present here results from the operating of this Front-End Module in the demonstrator system installed in the ATLAS test-beam at CERN.
One of the many challenges when building detectors for the Large Hardron Col- lider (LHC) is to construct a first-level trigger able to efficiently select potentially interesting events. Therefore the level-1 calorimeter trigger system for the ATLAS experiment must identify isolated electromagnetic clusters, hadronic jets and missing transverse energy, using signals from over 7000 electromagnetic and hadronic calorimeter trigger towers. These signals are transported over a distance of about 60m from the calorimeters to the Front-End System, the first processing stage in the data ow of the level-1 calorimeter trigger electronics. The Front-End system architecture includes different functional components requiring modern design techniques and advanced technologies, which need to be evaluated before the final trigger system can be manufactured. Therefore a demonstrator Front-End Module (FEM) was designed and tested in an extended demonstrator project.
To achieve a compact design of the Front-End system an Application Specific Integrated Circuit (Front-End ASIC) was designed. This ASIC contains the digital preprocessing for the level-1 trigger, a Look-Up Table (LUT) for energy calibration and a Bunch-Crossing Identification algorithm (BCID). It also includes a derandomizer buffer in which the data corresponding to a level-1 trigger accept are stored before being read out. This element is necessary to accommodate the maximum instantaneous level-1 trigger rate without introducing dead-time to the system.
Four Front-End ASICs are embedded in a four-channel FEM as shown in figure 1. The ASICs are controlled by a Field Programmable Gate Array (FPGA), which provides a high level of exibility for the data acquisition software to read out and to program the Front-End Module. The interface between the Front-End Module and the data acquisition software is a dual-ported memory which is directly accessible over the VME bus. It is used to send commands via mailbox interrupts to the FPGA and executes programs which were written to it. In the demonstrator system the Front-End Module is located between a Flash Analog to Digital Converter (FADC) digitising 36 channels of prototype calorimeter data at 40MHz and a Cluster Processor Module (CPM). It transmits the digitised and preprocessed calorimeter signals serially to the CPM over Hewlett-Packard electrical G-links running at 800Mbits/s. Part of the current test-beam programme is to study the data capture during run time and to test the high speed serial data transmission to the next board in the data chain. Results from the first test-beam studies in July and August 1997 will be presented.
Maciej Gorski a), Ignacy M. Kudla a), Krzysztof T. Pozniak
b)
a) Warsaw University, Institute of Experimental Physics, Hoza69,
00-681 Warsaw, Poland (kudla@hozavx.fuw.edu.pl)
b) Warsaw University of Technology, Nowowiejska 15/16,
00-665 Warsaw, Poland (pozniak@vxdesy.desy.de)
The CMS detector will have a dedicated subdetector (RPC chambers) to identify muons, measure their transverse momenta pt, and determine the bunch crossing from which they originate. Trigger algorithm is based on muon track search and classification in raw data from the RPC chambers. A huge interconnection network is needed to fulfil this task. It can be built in the control room only, far away from the detector.
To reduce the cost of the links transmitting data from the detector to the control room, a compression/decompression system is proposed. Only the non zero RPC data are sent via this system. The idea of such a system and its limitations are discussed. High Speed Data Transmission and Compression for the CMS RPC Muon Trigger
Very low rate of the RPC chamber data allows us to propose a compression/decompression data system to transfer only the non zero RPC data from the detector to the control room. Original structure of the data is restored from the string of frames received through data link with additional latency on the control room side. It means that, in normal situation (link not overloaded), the data on the control room side are identical to the detector data but are delayed by a fixed number of clock periods. This full form of the data is necessary to fulfil the muon finding and measuring algorithms. The data rate constraints are discussed.
A set of compression (LMUX) and decompression (LDEMUX) circuits allows us to reduce the number of links needed to transfer RPC data from the detector to the control room by a factor of 4 in comparison to the number of links needed to transfer all (even empty) detector's data.
On the detector side, the RPC data are synchronized to the bunch crossing. These synchronized data (40 MHz) are scanned by the LMUX device. LMUX is build using input FIFO data buffer and output transmitting multiplexer. Subsequent registers of FIFO store non empty detector data and corresponding delay information (in terms of bunch crossings).
The sending multiplexer transmits the first non empty data, or special code if data were zero. Non empty data are send in groups of bits (data_partition) and are completed with the delay code (time_partition). A special code is send if the FIFO is full (in this case data will be lost). The latency of the LMUX device is fixed, and equals 2 bunch crossings.
On the control room side, the transmitted data are analyzed and restored to the original (synchronised detector data) shape by the LDEMUX device. The latency of LDEMUX is fixed and includes the maximum number of data_partition plus 2. When the compression/decompression system is overloaded the control room's data can be set by default to zero or to a programmed value.
Both devices incorporate the control and test parts allowing to monitor the data quality.
Altera implementation and tests of these LMUX/LDEMUX are reported.
The simulation of ASIC (standard cell) implementation of the LMUX/LDEMUX are shown as well.
A. RACZ
CERN
The logical model of the CMS front-end readout chain is described in a behavioural way. Although all the sub-detectors are intrinsically different, they must all obey to a common logical description. Then this conceptual harmony can be extended to the physical implementation. Such a standard approach is valuable during all the life time of the experiment from early design specifications up to final integration and maintenance. In the intermediate phase of prototyping, VME is used as the front-end readout bus. For maximum performances, a hardware programmable sequencer has been developed to move data over the bus : its capabilities are presented.
The first part deals with the logic behaviour of the front-end systems in CMS and their access links in order to control them and to extract the data. A minimum set of generic features has been identified and all front-end systems must be compliant to it. Among the generic features are : transformation of the physical signal to an electric signal/data, retention of this data during the latency of the level1 trigger, storage of a lv1 selected data in a derandomizer... Continuing downstream, the Front End Driver (the receiving element of the front-end systems data or FED) is described. The FED is the entry point of the CMS DAQ. Its functionalities are listed in a generic way and a logical partition of the FED is presented : this partition allows a unique design for all the CMS sub-detectors taking into account the specificities of each sub-detector. This unified approach is of first importance for system integration and maintenance. The next element of the DAQ is the Dual Port Memory (DPM) that will receive the event fragment of the FED through the Front-End Bus (FEB). In the early phase of prototyping, VME64 is used as the FEB. A dedicated data mover sitting on the DPM has been developed and constitute a high performance VME data acquisition engine : its programming capabilities and performances are presented.
J.F. Renardy
The calibration of the Atlas liquid argon calorimeter requires a test pulse command finely adjustable with respect to the local 40MHz clock. The present TTC system has not foreseen such a requirement. This paper describes one solution to implement the needed signals with a standard TTC receiver chip and presents the performances obtained.
To extract the electromagnetic energy from the digitization of the Atlas liquid argon calorimeter signals, one needs to know the shape of the pulses at the output of the shapers. The measurement of this pulse shape is done by shifting the digitization points (i.e. the 40MHz clock) with respect to a calibration pulse. The test pulse command and the 40MHz clock are generated locally, in the front-end crate, by a TTC receiver. The TTC system was designed to compensate for clock distribution misalignments and therefore can only produce signals synchronous with the local 40MHz clock. It is nevertheless possible to use some features of the TTCrx chip and some extra logic to generate a test pulse command signal with the required timing.
We present such an implementation of the fast signal distribution for the Atlas liquid argon calorimeter. It is composed of a standard TTC system supplemented with dedicated VME modules, both on the sender and on the receiver sides. The sender produces the A and B signals needed by the TTC system. The A signal is derived from an external trigger input. The B signal carries the standard broadcast for the bunch counter reset as well as new broadcasts for the generation of the test pulse command. On the receiver side, one uses a standard TTCrx chip producing the 40MHz clock, the bunch counter reset signal and the level 1 accept pulses. An extra logic converts the additional broadcasts to a raw signal and re-synchronize it to the auxiliary clock of the TTCrx chip, producing the requested test pulse command. In addition, the sender logic takes care of sending all the addressed commands needed for a correct configuration of the TTCrx chip.
These VME modules are presently being tested. Results of these tests will be reported at the workshop.
Werner Riegler (CERN)
For the ATLAS MDT electronics group
The ATLAS muon system will be equipped with high pressure drift tubes aiming for excellent position measurement of the muon tracks.Detailed simulations of the detector response to charged particle tracks made the study of all the pieces of information, contained in the wire chamber signal, possible. Front-end schematics as well as ideas how to encode several pieces of information into one output channel are presented.
The ATLAS muon spectrometer will use high pressure drift tubes to measure muon tracks with a spatial resolution of 60um persingle tube. The tubes are 3cm in diameter filled with 3 bars of an Ar/N2/CH4 gas mixture. A 50um wire sitting in the centre of thetube is put to high voltage. Muons traversing the tube ionize the gas along it's track, the ionization electrons drift towards the wire along the electric field lines, form an avalanche at the wire andinduce a current signal that is amplified by dedicated electronics. The time of the pulse arrival is stored and from this measured drifttime one can derive the distance of the muon track from the wire.
Due to the high background rates in the ATLAS spectrometer the possible degradation of the chamber performance (aging) due tohigh amounts of charge deposits on the wire is a serious problem. To minimise the aging effects one has to operate the chambers at a verylow gas gain which can degrade the performance significantly.
Also the pile-up of signals and the resulting inefficiency can degrade the muon chamber performance.
Traditionally one is only interested in the leading edge of the induced signal giving the drift time of the electrons.
In addition to the leading edge time there is more information contained in the signal which can be used to avoid the degradation of the chamber performance due to the difficult environment:
1) The signal rise time, measured e.g. by a short gate ADC, can be used to correct for time slewing effects corresponding to degraded resolution due to charge fluctuations in the leading edge of the signal.
2) The trailing edge of the signal corresponds to signals from electrons created close to the tube wall, so the trailing edge time has a fixed latency to the bunch crossing. This information can be used to reject out of time hits.
3) Using a second discriminator with a high threshold one can identify piled up signals which helps to increase the tube efficiency.
The ATLAS MDT electronics is capable of creating all thisinformation on the front-end.
Since reading out all the information in parallel would require more than one channel per tube we developed ways to encode parts of the information into one single output.
The selectable readout options are:
1) leading edge + trailing edge
2) leading edge + charge information
3) leading edge + charge information + high threshold leading edges
Detailed simulations of the response of this electronics scheme to charged particle tracks as well as comparison to test measurements will bepresented in this talk.
Gyorgy Rubin, Peter Csato, Tivadar Kiss, Zoltan Meggyesi, Janos Sulyan, Laszlo Szendrei, Gyorgy Vesztergombi (RMKI, Budapest)
Gabor Harangozo, Jozsef Harangozo, Istvan Novak, Sandor Szilagyi (BME, Budapest)
Pierre Vande Vyvre (CERN, Geneva)
In this paper we present the development of the ALICE Detector Data Link (DDL) prototype which has been developed by RMKI, BME and CERN for the special needs of the ALICE experiment. This link provides high-speed transmission of data blocks (e. g. event data, thresholds, pedestals) in both directions between the front-en electronics and the data-acquisition system. The DDL can also be used as a transmission medium for the remote control and test of the front-end electronics during the normal operation and for the remote debugging during the system integration of the ALICE detector. A first prototype will be used in the ALICE-TPC test system.
The DDL will interface the front-end electronics (FEE) of all the sub-detectors to the read-out receiver cards (RORC) of the data-acquisition system. The source interface units (SIU) are connected to the FEEs and placed inside the detector. The destination interface units (DIU) are connected to the RORCs, located in the counting room about 200 meters from the detector. The two DDL interface units are connected through the physical medium which is a duplex optical fibre. The complete ALICE data-acquisition system will include several hundreds of DDLs.
The main data flow will take place from the FEE to the RORC. The DDLs shall be able to read-out the complete ALICE events (40 MB) in less than 2 ms, transmitting event data from the FEE to the RORC with a detected bit error rate of < 10-15. Each DDL shall be able to transmit data at a rate of 100 MB/s. As the zero suppression algorithm requires downloading blocks of data into the FEE, a throughput of 10 MB/s is needed in the opposite direction.
Both the FEE and the SIU shall be remotely controlled by the RORC through the DDL, since their placement inside the detector will not allow using any other cabling apart from the DDL medium. Therefore, commands and status information shall also be transmitted between the FEE and the RORC.
Since the SIU is located inside the detector, the requirements for the lifetime (> 10 years), the power consumption (< 5W) and the footprint (< 50 cm2) of this unit are key issues. More strict requirements have been identified for the ITS sub-detector where radiation tolerant electronics is needed and the maximum footprint of the SIU shall be less than 15 cm2.
To achieve the high reliability of the experimental apparatus, efficient test of all the sub-systems shall be provided. The DDL shall allow to test the FEE remotely by using JTAG Boundary-scan Testing procedure. The DDL itself shall also have a powerful self-test mode.
The DDL protocol consists of four layers: the DDL interface layer (most upper layer), the signalling and framing layer, the coding layer and the physical layer.
The DDL interface layer is described in the Interface Control Document. The definition includes the physical and electrical description of the interface units, the interface signal description, the definition of the information structures, the interface protocol and the interface timing.
A limited subset of the FC-PH FC(2) standard is used in the specification of signalling and framing layer. However, in this specification mainly DDL specific solutions are used, like ordered set definitions, frame structure and flow control.
The Fibre Channel standard (FCS) has been chosen for the first implementation of the DDL. The coding layer is defined in the FC-PH FC(1) standard, while the physical layer in the FC-PH FC(0) standard.
The interface units (SIU and DIU) consist of two main functional part: the protocol chip and the media interface. In the protocol chip the three upper layers of the DDL protocol have been implemented, while the media interface realises the most lower layer.
For the functional, performance and stability tests of the DDL a test setup has also been developed. It consists of the following elements: a front-end emulator, a Fibre Channel line monitor, a read-out receiver card and the test software.
J.M. Seixas, L.P. Caloba, A.S. Cerqueira
COPPE/EE/UFRJ, C.P. 68504, Rio de Janeiro 21945-970, Brazil e-mail:
seixas@lacc@ufrj.br Fax: 55-21-2906626 Tel: 55-21-2807393
CERN - PPE division. e-mail:seixasj@vxcern.cern.ch
An active adder for building the trigger tower signals required by the first-level trigger system for the scintillating tile calorimeter is described. It is designed to handle fast signals (50 ns width) that have to be linearly combined over a wide dynamic range (10 bits). Five differential signals coming from the three sampling layers of the calorimeter can be combined and the adder's output is also differential. Successful tests of the proposed circuit interfacing with shaper boards currently being used for testbeam purposes are also reported.
The first level trigger system requires trigger tower signals from the calorimeter subsystems. The trigger towers are built by summing the sampling layers of the electromagnetic and hadronic sections, with a granularity of 0.1 x 0.1 in eta and phi (for rapidities up to 2.5). For the Tiles calorimeter, such requirement in the barrell region translates into the summation of five signals from the three sampling layers of the detector: two from the first layer, other two from the second layer and one signal from the last layer. Due to compatibility reasons, the 5-input topology for the level-one adder will be kept for the overall detector. An analog summation scheme is described in this paper.The design goal is to comply with input and output requirements coming from the subsystems which interface with the adder. Signals to be summed are received by the shaper unit [1], so that the adder should support differential input signals transported by 50 ohms shielded pair cables. In terms of signal speed, the shaper provides 50 ns FWHM signals. Signals would be derived from the low gain shaper signal, which implies a full scale amplitude of 1 Volt. As signals from different depths of the calorimeter are to be combined, timing the different signals within 2 ns may be required. The supply voltages for the adder follow the shaper needs, so that +/- 5 Volts are used. The adder boards would make up the outer layer of the 3-layer structure in the drawer system of the calorimeter. The trigger signals would be routed along this layer to the patch panel at the end of the drawer. On the other hand, the adder output is effectively the connector where the level-one trigger signal leaves the detector. Trigger signals are expected to be transmitted by using shielded twisted-pair cables. Further level-one trigger requirements include 10-bit dynamic range and linearity up to the full-scale amplitude into the ADCs (2.5 Volts), among others. The proposed circuit is DC biased at 5 mA for each channel and signals are AC coupled to the adder's input. The differential input signals are coupled to the summing point by means of wideband transistors arranged in a differential configuration, so that signal speed is not deteriorated. The output stage comprises an output offset adjustment and current mirrors for transmitting the summed signal differentially to the output connector. The circuit was tested in combination with shaper units currently being used in testbeams. Preliminary results are encouraging. The linearity was found to be 1.4% for a voltage swing better than 3 Volts. Signals were added without any noticeable distortion in terms of signal speed and the gain for each channel agreeded within the 5% limit of the tolerance of the resistors being used. The crosstalk was better than 60 dB and noise was estimated to be smaller than 1 mV.
[1] - A Low Noise, High Rate Shaper for the Tilecal Detector. K. Anderson et al. First Workshop on Electronics for LHC Experiments, Lisbon (1995) pp 261.
A. Kugel, J. Ludvig, R. Männer, K.-H. Noffz, S. Rühl,
M. Sessler, H. Simmler, H. Singpiel, R. Zoz
Universität Mannheim, Germany
J.R. Hubbard, P. Le Dû, M. Smizanska
Centre D'Etudes Nucleaires De Saclay, France
There are several different concepts for the ATLAS Level-2 trigger under investigation, all of which have to cope with the following challenges
These above problems could be resolved by a hybrid trigger combining an FPGA-processor and a processor-farm. The inserted FPGA-processor layer executes simple reconstruction algorithms and applies loose physics selection criteria. These criteria already reject ³ 80% of the events with a high - pt trigger and reduce the bandwith by a factor of 6 in regard to the full scan TRT. This would scale down the farm and strongly reduce the networking requirements.
The FPGA-processor layer and the farm together build a cost e ective hybrid solution for the level-2 trigger.
S. Dasu, M. Jaworski, J. Lackey, W. H. Smith
University of Wisconsin, Madison, WI, USA
The CMS level-1 trigger system carefully sifts the 40 MHz data to retain only interesting physics signals at 100 KHz level while discarding the well known QCD background. The level-1 calorimeter trigger electronics discussed here is designed to identify signatures for high energy electrons, photons, neutrinos and jets. The electron/photon trigger algorithm involves local isolation cuts requiring sharing of data amongst neighboring regions. The jet and neutrino trigger algorithms require additions of energies from large number of trigger towers. Both the algorithms are implemented in high-speed custom integrated circuits to satisfy the required short latency for trigger decision. We report about prototype construction and testing program which was instituted in order to demonstrate the crucial features of this trigger system. We fabricated prototype adder ASICs which sum eight 10-bit signed numbers in a total of 4 clock-steps at 160 MHz. These ASICs built by Vitesse in GaAs technology, chosen for its speed and ECL output capability, have been tested to work at 200 MHz, well above our specifications. At the heart of the trigger system is a custom "backplane" which provides point-to-point links for data sharing between the various cards at 160 MHz. In order to test the feasibility of operation at high frequency we built a complete prototype backplane with 1419 differential point-to-point links. The clock signals on the backplane show rise and fall times below 1 ns with reasonable signal levels even when measured at the farthest card slot. We will discuss the performance of this backplane, the test cards that are under being manufactured and the Adder ASIC.
The CMS detector for the Large Hadron Collider (LHC) presents an extraordinary challenge for its trigger and data acquisition system. Its trigger system must carefully sift the 40 MHz data to retain only interesting physics signals at 100 Hz level while discarding the well known QCD background. The CMS solution to this problem is implemented in two physical levels, one based on custom electronics and the other relying upon commercial pro- cessors. The level-1 system uses only coarsely segmented data from calorimeter and muon detectors, while holding all the high resolution data in pipeline memories in the front-end electronics, to produce a trigger decision in 3 Ms. Level-1 triggered events at 100 kHz rate are sifted further in higher levels of triggers implemented as software filters. We discuss here the level-1 calorimeter trigger electronics which is designed to identify signatures for high energy electrons, photons, neutrinos and jets. The electron/photon trigger algorithm involves local isolation cuts requiring sharing of data amongst neighboring regions. The jet and neutrino trigger algorithms require additions of energies from large number of trigger towers. Both the algorithms are implemented in high-speed custom integrated circuits to satisfy the required short latency for trigger decision.
The barrel and end-cap calorimeter trigger system is implemented in 18 crates shown in Figure 1, each handling 256 trigger towers. Data from 32 ECAL and HCAL trigger towers arrives on fiber optic cables in serial form at 1 GBaud to the back side of the eight Receiver cards plugged into the rear of the crate. After optical-to-electrical and serial-to-parallel conversion the data are transferred through the card to the front side of the Receiver cards. Data are synchronized and verified to be valid using the error detection Hamming code. Linearized data in parallel form are shared at 40 MHz with the neighboring crates after this synchronization step. The entire system operates in lock-step after this stage at 160 MHz. The energies are then summed to 4 x 4 trigger tower regions using custom Adder ASICs on the Receiver card. The heart of the crate is a central "backplane" which provides data sharing at 160 MHz. Data for the electron isolation logic which includes both the data received on the fiber and that received on inter-crate cables are transferred to the Electron Isolation cards plugged into the front-side of the "backplane". The 4 x 4 sums are transferred to the Jet/Summary card plugged into the center of the backplane on the front-side of the crate. The Electron Isolation card implements its algorithm in a custom integrated circuit. The candidate electrons are ranked and top candidates are passed to the Jet/Summary card. The Jet/Summary card sorts the electron and jet candidates in the crate to output the top four candidates of each kind on a cable to the global trigger. It also calculates sums of Ex, Ey and Et in the crate using Adder ASICs.
We report about the prototype construction and testing program which was instituted in order to demonstrate the crucial features of this trigger system.
We fabricated prototype adder ASICs which sum eight 10-bit signed numbers in a total of 4 clock-steps at 160 MHz. These ASICs built by Vitesse in GaAs technology, chosen for its speed and ECL output capability, have been tested to work at 200 MHz, well above our specifications.
At the heart of the trigger system described above is the custom "backplane" which provides point-to-point links for data sharing between the various cards at 160 MHz. In order to test the feasibility of operation at high frequency we built a complete prototype backplane which can house up to eight Receiver and Electron Isolation card pairs, a Clock card and a Jet/Summary card . On one end of the backplane two standard 6U VME card slots are also provided. The backplane uses a single 128-pin DIN connector to implement the 32-bit VME and a 340-pin AMP connector to implement the point-to-point links in the custom card region of the backplane. There are 1419 differential point-to-point links on the backplane between the various cards. The backplane is constructed with five ground and power planes and five signal layers with the differential pairs held to the same layer.
A simplified clock card which provides the 160 MHz clock, reset and synchronize signals has also been fabricated. This card contains adjustable delays so that the phases on all the seventeen cards can be individually adjusted to match. The clock signals on the backplane show rise and fall times below 1 ns with reasonable signal levels even when measured at the farthest card slot.
A prototype receiver card, implementing all the 32 EM and Had. channels, with the memory look-up-tables, the Adder ASIC and the backplane drivers is being built. The purpose of the card is to test both the signal integrity on the backplane and the Adder ASIC operation. The card implements the VME control and JTAG boundary scan capability. We are also making a prototype Electron Isolation card so that the data sharing tests can be carried out.
We conclude that these prototype efforts indicate that the conceptual design for the CMS calorimeter trigger is feasible.
S Sumorok
Event building for Run II on the CDF experiment at Fermilab is specified as upto 300 events/s into Level 3 with an average event size of about 150 kB. The event must be assembled from fragments originating from about a dozen readout sources, with fragment sizes in the range from 10 to 30 kB, implying that individual links must function with speeds of upto 10 MB/s. We report on preliminary studies conducted at CDF with an ATM based event builder test system. Such a system is a possible candidate for the CMS experiment at LHC.
Asynchronous Transfer Mode (ATM) technologies, which have been undergoing considerable development in the telecommunications industry are a promising option for building such events. The test system for the CDF upgrade is built around a FORE Systems ASX-100 non-blocking ATM switch with 13 K cell output buffers. The switch is currently equipped with 8 155 Mbps input/ouput ports but is expandable upto 64 such ports. Each port is connected to a PowerPC based VME single board computer running VxWorks 5.2. These computers can either act as Scanners, which read data from the detector front ends and send it to the switch, or Receivers, which combine the fragments into events for the Level 3 System. A ninth PowerPC computer is used as a Scanner Manager and is connected to the other computers via the command network, in this case a Systran SCRAMNet ring of VME reflective memories.
The most basic tests involving the ATM components are those in which N sender computers perform uncoordinated rapid-fire packet transmissions to each of M receiver computers. Results are presented for 1 to M with M equal 1 through 7, 2 to 2, 3 to 3 and 4 to 4 senders and receivers respectively. The expected scaling is observed which allows extrapolation to the larger system required for the CDF Run II readout.
Traffic shaping is studied and a comparison of "rate division" and "barrel shifter" algorithms made. The "barrel shifter" plateaus around 450 events/s. The "rate division" method reaches 1000 events/s which then falls slowly with increasing message traffic due to CPU saturation. A computer upgrade would likely further increase the event throughput. In a 4 to 4 system sending 32 kB events each link is carrying more than 13 MB/s where the Run II target is 10 MB/s. The event thoughput is 450 events/s with event fragments twice the size of the average largest fragment for Run II and no cell loss was observed.
L. Berger 1 , R. Nóbrega 2 , J.C. da
Silva 2 , J. Varela 2,3
1- Tecmic, Lisbon;
2- LIP, Lisbon; 3- CERN
We present the principles of a method for trigger data synchronization at LHC. Themethod makes use of the LHC bunch gap and allows a resynchronization of the data every LHC orbit (88 ms). It relies on the distribution by the TTC system of a signal synchronous with the first bunch in the orbit, and is implemented by a couple of circuits, Sync Tx/Rx, in each trigger link. We report on the test of the first prototype implementation.
The CMS trigger system can be viewed as a massive parallel processor that computes local trigger objects, followed by a tree like structure that selects the highest rank objects in the detector or performs global energy sums. The entire system works in synchronous pipeline mode, processing events at the 40 MHz LHC rate.
The system is based on the assumption that, at every processing stage, the data are synchronized and belong to the same bunch crossing. This goal has to be achieved without making use of bunch crossing identifiers attached to the data, which would imply a non acceptable complication of the trigger system design.
In this paper we propose a method for the synchronization of the trigger data that builds on the ideas presented in reference [1]. The method takes profit of the gaps in the LHC bunch structure (sequence of clock cycles without particles). During the largest gap (127 clock periods) occurring every 89 ms, each transmitter sends synchronization data which is used by the receivers to adjust their phase. The start and the end of the synchronization gap is identified by commands send by the TTC System [2]. To implement the method, two specialized circuits, a Synchronization Transmitter (Sync TX) and a Synchronization Receiver (Sync RX), are needed in the trigger data links .
Due to different flight paths to different regions of the detector, the various Trigger Primitive Generator (TPG) in the front-ends are not necessarily synchronized with each other. In addition, the lengths of the fibers from the TPGs to the Regional Trigger Processors (RTP) could be different. As a result, data corresponding to the same crossing arrive at different times at the RTPs inputs . The proposed synchronization method uses FIFOs at the end of the transmission lines to re-synchronize the data. The key points in the FIFOs operation are the following: i) after a clear, the first data entering every FIFOs correspond to the same crossing ; ii) the readout of the FIFOs is controlled by a common signal arriving simultaneously to every channel.
Re-synchronization actions are performed at every LHC orbit using about 32 clock periods out of the 127 gap length. The circuits have monitoring mechanisms which allow to identify any loss of synchronization. Phase adjustments between the TTC synchronous commands and the trigger data are computed based on statistical data accumulated in the Sync Tx. A few minutes of running is in general enough to determine all time settings needed for a proper operation of the trigger.
[1] M. A. Thompson, 'SDC Link Word Synchronization', SDC Note
SDC-93-536, June 23, 1993.
[2] RD12 Status Report, CERN/LHCC 95-26, April 24, 1995.
The NA57 Collaboration
Presented by O. Villalobos Baillie
School of Physics and Astronomy
The University of Birmingham
The NA57 experiment at the CERN SPS uses a new trigger system in which certain features which will later be implemented in the ALICE experiment can be tested. In NA57, it is envisaged that physics measurements will be carried out in parallel with tests of a variety of ALICE prototypes. The triggering and readout of physics detectors will be performed allowing independent dead times for each sub-detector, so as to make effcient use of the beam time. Detector specific past- future protection and extensive monitoring and diagnostic features are provided. We describe the design features for this system, and present test results.
The ALICE experiment aims to measure heavy ion and pp collisions at the CERN LHC. The trigger system for this experiment, which has been described in a previous publication [1], uses signals from three different detector systems: multiplicity signals from Forward Multiplicity Detectors (FMD), zero degree energy measurements from a calorimeter system (ZDC) and a dimuon selection. These select central collisions, which have a high cross section, and events containing dimuon candidates of different types, some of which are quite rare. The trigger system will use a system of dead time management in which different sub-detectors can have independent dead times, in order to maximize the effective luminosity for rare event classes. In addition, large past-future protection intervals must be used to guard against pile up in the Time Projection Chamber (TPC), which has a drift time of 100 us.
The NA57 experiment at the CERN SPS uses a new trigger system in which these features can be tested, adapted to the different requirements of a fixed target experiment. The incident beam flux rate will be up to 10 MHz. The principal physics aim of the experiment is the measurement of hyperon spectra using a silicon pixel telescope. However, the physics measurements will be combined with a variety of independent tests of ALICE detector prototypes in parallel with normal data taking. The requirement of simultaneous triggering and readout of physics detectors and test detectors will be handled using a dead time management system similar to that envisaged in the ALICE experiment. In addition, independent past-future protection intervals can be set for each sub-detector in a way which is equivalent to the ALICE requirement, and priorities can be allocated for different trigger types through independent scaling factors. The trigger is implemented in VME standard, using programmable trigger matrices which allow the specifications of any logical combination of the input signals as a valid trigger. A fast trigger logic defines a beam signal, which is used to latch the trigger inputs and the busy status at the start of the trigger. For each trigger type a set of required sub-detectors is specified, and the trigger is blocked if any of this sub-detector set is found to be busy. In order to monitor trigger performance, scaler count the input rate for each trigger input, and the dead time contribution from each sub-detector is clocked. In addition, the contents of the input register are stored for each trigger, together with the trigger output in order to allow software trigger verification. Delays for synchronization of input signals are programmable. Two outputs for oscilloscope monitoring are foreseen, which can be used for any two input signals selected by computer control. The design features for this system are presented, together with some test results.
[1].H. Beker et al., The ALICE Trigger System Proc. 2nd Workshop on Electronics for LHC Experiments, Balatonfured, Hungary, 1996. CERN/LHCC/96-39, p. 170.
G.Feofilov, O.Stolyarov, F.Tsimbal, L.Vinogradov, F.Valiev
St.Petersburg, Russia, Institute for Physics of St.Petersburg State
University
V.Kasatkin, V.Kuts, O.Zhigunov, V.Platonov
St.Petersburg , Russia, Central Scientific c Research Institute
"Granit"
W.Klempt, A.Rudge
CERN, Geneva, Switzerland, European Organization for Nuclear Research
V.Lenti
Bari, Italy, Dipartamento di Fisica dell'Universita and Sezione INFN
O.Villalobos Baillie
Birmingham, United Kingdom, School of Physics and Astronomy
L.Efimov
JINR, Dubna, Russia, Joint Institute for Nuclear Research
We present design details and new measurements of the performance of fast electronics for the Forward Multiplicity Detector (FMD) for the ALICE experiment, based on Microchannel Plates (MCP). These detectors give the first trigger decision in the ALICE experiment. Fast passive summators are used on the detector for linear summation of up to eight isochronous signal channels from MCP pads. We present measurements of the performance of these summators, working in the frequency range up to 1 GHz. New low noise preamplifier , based on the Rudge transimpedance preamplifier , have been built to work with these summators. The new design shows a considerable improvement in performance with the usable frequency range extended up to 1 Ghz.
The first trigger decision in the ALICE experiment is made using the Forward Multiplicity Detector (FMD) system based on Microchannel Plates (MCP). This system provides information on (i) multiplicity in a given rapidity range, and (ii) primary vertex z location, while (iii) permitting the rejection of beam gas events. The signals from these detectors allow very precise timing and the pulse height is proportional to the multiplicity. In order to use the signals in the trigger, it is necessary to sum signals from many pads, while preserving the timing precision and summing the pulse heights with good linearity. We present the design and performance tests of the first industrial production prototypes for the fast readout electronics for the FMD-MCP detector.
Two types of fast passive summators based on UHF microelectronics design are tested. These are a development of the prototype design for which results were presented one year ago[1]. They are capable of providing linear summation of up to 8 isochronous signal channels over a wide dynamic range. The working frequency range is up to 1GHz. The level of cross-talk was found to be about 60 dB for charge measurements in neighbouring channels.
One of the peculiarities of the UHF passive summator is the theoretical complete absence of noise. We found no deterioration in the S/N ratio compared to the single channel case. Results of tests using both a pulse generator and real MCP signals are presented.
New low-noise preamplifier , matched in impedance with the output signals from the passive summators, have been built. Two types of preamplifiers are being References considered: (i) for precise timing, and (ii) for charge measurements. Type (i) based on the Rudge transimpedance preamplifier [2] was industrially produced and tested. It has 50 Ohm input impedance. Results show a considerable improvement in the performance, with the usable frequency range increased up to 1 GHz. Tests of the complete chain including passive summator and fast preamplifier are also presented.
[1]. L.G.E mov et al., Proceedings of the 2nd Workshop on
Electronics for LHC Experiments, Balatonfured, September 23-27,
p.166-169, 1966; CERN/LHCC/96-39
[2]. A.Rudge , Nuclear Instruments and Methods,A360(1995)169-176
Torsten Wildschek, Alexander Kluge
The track finder receives trigger primitives from drift tubes in the barrel and from cathode strip chambers in the forward muon system. It assembles those trigger primitives to tracks, assigns transverse momentum, direction and quality to tracks and transmits these data to the global muon trigger. We present the track finder algorithm, hardware implementation and the status of the FPGA prototype.
The track finder receives input from two sources: from DTBX (drift tubes with bunch crossing identification) in the barrel and from CSCs (cathode strip chambers) in the forward region. Either system outputs trigger primitives representing a track segment, which consists of position, bend angle and quality tag. In the barrel part up to two track segments can be output per chamber, in the forward up to three per logical sector in either projection. Those track segments are transmitted to the track finder at a fixed delay after the bunch crossing from which the tracks originate.
The track finder assembles trigger primitives to tracks, assigns transverse momentum, direction and quality to the found tracks and transmits these data to the global muon trigger.
Track segments are joined to tracks by pairwise matching. If 2 track segments from different stations are found to originate from a single track they form a t rack segment pair; if one of those track segments is found to be compatible with a third segment from a station other than the first two a track segment triple is formed. A fitting forth track segment yields a quadruple. All the comparisons required are carried out in parallel. Each track belongs to a track class, defined by the combination of stations contained in this track. Those track classes are ordered by quality - track class 1 with all 4 stations has highest quality.
Pairwise matching is carried out by extrapolation. The measured bend angle is used to extrapolate a track segment to a different station, defining a window in the latter station, within which a matching track segment may be found.
Several selection steps are required to reduce the number of ghosts created in this process. If one track crosses the chamber, more than one track segment can be output owing to showers in front of the chambers and delta rays within the chamber. These spurious track segments give rise to ghost tracks. One track segment may belong to only one track. If two tracks have a track segment in common, they are deemed incompatible and only one of them will be passed to the next step. The selection is based on track segment quality and track class.
The overlap region, a region in eta where a track may give hits both in the barrel and the endcap chambers, requires special treatment in track finding.
Once a track has been formed and found to be pointing to the vertex, the unique relationship between its bend angle and transverse momentum is used for p_t assignment. Transverse momentum is used for a final selection stage, and up to four tracks per eta-wheel with their p_t, direction values and a quality tag are passed to the global muon trigger.
At present, a prototype of one sector of the track finder is being assembled and its evaluation is under preparation. We will present the results of this evaluation.