# Title: CBC I2C Register settings. The measurement used to choose biases are explained in https://indico.cern.ch/event/650691/contributions/2647623/attachments/1488040/2313137/CBC3_FE_measurements.pdf # Fields: Page(3 for name) Address(name) Value # FieldTypes: int int(string) int 3 FcCntrlCompBetaTrigLat.trig_lat 200 3 FcCntrlCompBetaTrigLat.beta_mult 0 3 FcCntrlCompBetaTrigLat.comp_hyst 0 3 FcCntrlCompBetaTrigLat.comp_pol 1 3 BetaMultiplierAndSLVS.beta_mult 5 3 BetaMultiplierAndSLVS.slvs_curr 7 3 Ipre1.curr 45 # The value chosen from the measurement 3 Ipre2.curr 80 # The value chosen from the measurement 3 Ipsf.curr 80 # The value chosen from the measurement 3 Ipa.curr 80 # The value chosen from the measurement 3 Ipaos.curr 45 # The value chosen from the measurement 3 Icomp.curr 40 # The value chosen from the measurement 3 VPLUS.vplus1 7 # Do not change this. Other values were not used in the simulation. 3 VPLUS.vplus2 7 # Do not change this. Other values were not used in the simulation. 3 HipAndTestMode.hip_count 0 3 HipAndTestMode.hip_supp 0 # 0: hip suppression enabled. set 1 to disable 3 HipAndTestMode.hip_src 0 3 HipAndTestMode.slvs_off 0 3 TestPulsePotentiometer.pot 12 # ~ 1 fC 3 TestPulseDelayGroup.delay 15 3 TestPulseDelayGroup.group 6 3 TestPulsePolEnAMux.tp_en 1 3 TestPulsePolEnAMux.tp_gnd 1 3 CAL_Ibias.curr 240 3 CAL_Vcasc.volt 63 3 PlStLogicSelAndPtWidth.pl_sel 1 # 0: sample, 1: or, 2: hip suppressed, 3: fixed pulse width 3 PlStLogicSelAndPtWidth.st_sel 1 # 0: sample, 1: or, 2: hip suppressed, 3: fixed pulse width 3 CoinWindowOffsets.ofst1 0 3 CoinWindowOffsets.ofst2 0 3 CoinWindowOffsets.ofst3 0 3 CoinWindowOffsets.ofst4 0 3 LayerSwapAndClusterWidth.lswap 0 3 LayerSwapAndClusterWidth.width 4 3 40MHzClockOr254DLL.dll 4 3 40MHzClockOr254DLL.test_out_40mhz_clk 0 3 40MHzClockOr254DLL.or254 0 3 40MHzClockOr254DLL.tpg 1 # clock to the test pulse do not bypass dll 3 FciAndError.fci_delay 0 3 MaskChannels.ch_001_008 0xff # set 0 to mask 3 MaskChannels.ch_009_016 0xff 3 MaskChannels.ch_017_024 0xff 3 MaskChannels.ch_025_032 0xff 3 MaskChannels.ch_033_040 0xff 3 MaskChannels.ch_041_048 0xff 3 MaskChannels.ch_049_056 0xff 3 MaskChannels.ch_057_064 0xff 3 MaskChannels.ch_065_072 0xff 3 MaskChannels.ch_073_080 0xff 3 MaskChannels.ch_081_088 0xff 3 MaskChannels.ch_089_096 0xff 3 MaskChannels.ch_097_104 0xff 3 MaskChannels.ch_105_112 0xff 3 MaskChannels.ch_113_120 0xff 3 MaskChannels.ch_121_128 0xff 3 MaskChannels.ch_129_136 0xff 3 MaskChannels.ch_137_144 0xff 3 MaskChannels.ch_145_152 0xff 3 MaskChannels.ch_153_160 0xff 3 MaskChannels.ch_161_168 0xff 3 MaskChannels.ch_169_176 0xff 3 MaskChannels.ch_177_184 0xff 3 MaskChannels.ch_185_192 0xff 3 MaskChannels.ch_193_200 0xff 3 MaskChannels.ch_201_208 0xff 3 MaskChannels.ch_209_216 0xff 3 MaskChannels.ch_217_224 0xff 3 MaskChannels.ch_225_232 0xff 3 MaskChannels.ch_233_240 0xff 3 MaskChannels.ch_241_248 0xff 3 MaskChannels.ch_249_254 0xff 3 Bends.cl_cntr_m7_m6h 0x99 3 Bends.cl_cntr_m6_m5h 0xaa 3 Bends.cl_cntr_m5_m4h 0xbb 3 Bends.cl_cntr_m4_m3h 0xcc 3 Bends.cl_cntr_m3_m2h 0xdd 3 Bends.cl_cntr_m2_m1h 0xee 3 Bends.cl_cntr_m1_m0h 0xff 3 Bends.cl_cntr_c_p0h 0x00 3 Bends.cl_cntr_p1_p1h 0x11 3 Bends.cl_cntr_p2_p2h 0x22 3 Bends.cl_cntr_p3_p3h 0x33 3 Bends.cl_cntr_p4_p4h 0x44 3 Bends.cl_cntr_p5_p5h 0x55 3 Bends.cl_cntr_p6_p6h 0x66 3 Bends.cl_cntr_p7 0x87 3 VCTH.vcth 550