Trip-T Front End Board Documentation Home
Power-On Configuration
FPGAs rely internally on SRAM, which is a volatile type of
memory. This means that when powered on the device will do nothing
until it has been programmed. The TFB, thus, has a EEPROM expressly
for this purpose. When powered on, the devices interact to transfer
the configuration design from the EEPROM to the FPGA.
Design Revisioning and Power On Reset
A special EEPROM containing two distinct design revision spaces was
chosen to prevent a working device from ever becoming inaccessible
through losing its ability to configure itself. Which revision is
booted from is controlled by the state of the revision address
pins. These in turn are driven by a standard dual D-Type latch. The
latch reset is driven by a schmitt triggered inverter with the input
connected to a C-R circuit between the 2.5V power rail. This
arrangement guarantees that the D-Type always powers up in a known
state and, this in turn, guarantees that the TFB always boots from
power up in the firmware contained in revision 0.
The time constant of the R-C circuit was chosen to be of the order of
10s for the TFBv3. It is thus not recommended to ramp the 2.5V (3.1V)
power rail in more than ~1 second. Please see
TFB Powering Rules (PDF)
for more information.
The POR line is also routed to the FPGA and used to hold the TFB in
reset for ~10s after power up. During this period of time, no
interaction with the TFB will be possible.