Trip-T Front End Board Documentation Home

DAQ Packet Description

ADC Packets

An ADC data packet is generated for each integration cycle, each one contains all the samples for all ADC channels for the integration cycle. It doesn't matter if a particular TripT is disabled, the data are sent anyway. This makes each of these packets fixed in size at 85 words long (170 bytes). This number comes from the fact that there are 4 ADCs each producing 10 bits/sample and 34 channels are read out giving 1360 bits per integration cycle. These are packed into 16 bit words for serialisation: (1360/16) = 85. The FIFO buffer in the TFB is large enough to hold all the data samples from the maximum number of integration cycles possible (tript limited to 23) and so, as long as the data are read out for each trigger, this cannot overflow.

It is important to note the correspondence between the ADC channels and the Time Stamp channel indices. In total, 34 channels are read out, this comes from 16 real channels, each with a high and low gain, plus 2 calibration channels. These are read out out first and last. The discriminators can only be connected to either the high or low gain channels are once. This has the consequence that the ADC code index for discriminator channel 0 will be 1.

The data may be unpacked using an algorithm such as: 

  void UnjumbleADCSamples(const unsigned short * aBuf,
  		          unsigned short * aA, 
			  unsigned short * aB, 
			  unsigned short * aC, 
			  unsigned short * aD){
        
    for(unsigned short i=0; i<17; i++){
      const unsigned long * lPtr=reinterpret_cast(&aBuf[5*i]);
           
      aA[2*i]=lPtr[0]&0x3ff;
      aB[2*i]=(lPtr[0]>>10)&0x3ff;
      aC[2*i]=(lPtr[0]>>20)&0x3ff;
      aD[2*i]=((lPtr[0]>>30)&0x3) | (((lPtr[1])&0xff)<<2);

      aA[2*i+1]=(lPtr[1]>>8)&0x3ff;
      aB[2*i+1]=(lPtr[1]>>18)&0x3ff;
      aC[2*i+1]=((lPtr[1]>>28)&0xf)|((aBuf[5*i+4]&0x3f)<<4);
      aD[2*i+1]=(aBuf[5*i+4]>>6)&0x3ff;

    }
  }
In this model, the raw output buffer of from the TFB is referred to by the pointer aBuf. The samples are separated into samples from distinct TripTs and placed in the buffers referred to by aA...aD respectively. The data occupy the least significant 10 bits, and the upper 6 bits are padded to 0. The destination buffers are the caller's responsibility. This code assumes:

sizeof(unsigned long)=4 bytes
sizeof(unsigned short)=2 bytes

to be true.

Time Stamp Packets

These contain the time stamp data. One packet is produced per channel for every channel on the board regardless of whether that channel is enabled. If no events generating time stamps occurred during the spill integration cycles, an empty packet is generated (this will be payload length 1 with just a CRC). It's this behaviour that resulted in the removal of the time stamp summary packet. An individual time stamp comprises 45 bits packet into three 16 bit words, padded to the 48 bit total with zeros. The first 2 words contain the 32 bit coarse time stamp as a binary value. The third word contains:
Bit Field Description
15:13 Padded to zero.
12:11 Fine time stamp. Each binary code represents 2.5ns.
10:5 binary encoded channel index: 0 = Channel 1, Trip-T A, 63 = Channel 16, Trip-T D.
4:0 Integration bucket index. Binary encoded integration window the time stamp belongs to.
The way to calculate the real time from the time stamp is:
Tclk * (Coarse Time) + (Tclk/4) * (Fine Time)


Where the clock period is nominally 10ns (100MHz). The packet length will thus be 3 times the number of time stamps, plus the CRC code.

Packet Output Policy

The packet sending policy of the TFB is programmable, and there are 2 modes: "Managed" and "Free". In the Managed mode the TFB will hold packets in a queue until a "packet send" trigger is received, and then it releases the first packet in the queue only. A trigger must be sent for each packet. ADC triggers are distinct from Time Stamp trigger. Each TripT time stamping circuit has its own queue must be triggered independently. In Free mode, the TFB will commit packets to the serial interface as they become available. It would also be possible to change the mode of operation from Managed to Free mid-operation. Additionally, there is a flag for each output queue, so that it's possible to operate, for example, the ADC data pipe in Free mode, but the time stamp circuit in managed mode.