Trip-T Front End Board Documentation/Serial Interface

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Serial Interface

Physical Layer

The physical layer comprises LVDS signalling over 4 twisted pairs using RJ45 connectors designed to be compatible with standard Ethernet cables. These lines are DC coupled, and the data are transmitted using an unbalanced encoding. The logical definitions of these lines are:

Clock Input to the TFB
Data Input to the TFB
Data Output from the TFB
Trigger input to the TFB

Link Calibration

Link is source synchronous for data transmitted from the RMM to the TFB. In the return direction there is now an automatic phase detection mechanism implemented in the RMM dealing with synchronization on a packet-by-packet basis.

Link Reliability

Reliability tests have been carried out at Imperial College using Cat5e cables up to 17m long. During the longest single run 10¹² bits were read out of the device and zero bit errors detected. It can be said that BER < 10^-11 with 99% confidence over a 17m cable.

Occasionally, some errors are observed. Single bit errors are most probably correctable using the CRC, but multi-bit errors are not.

Extrapolating this performance to a system with 1000 (identically performing) TFBs, the expectation error rate for single bit errors would be approximately one every 2000 triggers.

Protocol Layer

A light-weight packet based protocol is used that supports the following features:

TFB Identity Verification
Up to 16 Logical Pipes
Variable Packet Size
CRC
Acknowledge generation

The serial interface operates like a (FWFT) FIFO to FIFO Interface and comprises a header, payload and a trailing 16 bit CRC code. Upstream and downstream packets are identical in structure, though have some differences with regard to field definitions. Since input data for the TFB is output data for the RMM and vice-versa, to avoid ambiguity I will refer to TFB input data streams as the UPSTREAM direction, and TFB output data streams as DOWNSTREAM. The packet structures are defined in the table below:

Upstream Packet Definitions (to the TFB)
Position in the packet	Name	Description
0	ID	(15:4)=TFB-ID. (3:0)=Logical Pipe ID
1	Reserved	(15:0)=Reserved
2	Command Packet	(15:1)=Reserved. (1)=Force Acknowledge
3	Reserved	Reserved
4	Length	(15:0)=Binary encoded payload length (number of 16 bit words, including CRC)
5 to (Length+4)	Payload
Length+5	CRC	(15:0) CRC: 16 bit, polynomial = (0 5 12 16)

Downstream Packet Definitions (from the TFB)
Position in the packet	Name	Description
0	ID	(15:4)=TFB-ID. (3:0)=Logical Pipe ID
1	Status	(15:5)=Undefined. (4:0)=Integration Cycle No.
2	High Spill Number	(15:0) = Spill Number (31:16)
3	Low Spill Number	(15:0) = Spill Number (15:0)
4	Length	(15:0)=Binary encoded payload length (number of 16 bit words, including CRC)
5 to (Length+4)	Payload
Length+5	CRC	(15:0) CRC: 16 bit, polynomial = (0 5 12 16)

Acknowledge Packet

An acknowledge packet may be generated in response to some input packet to the device. Acknowledge packets come from logical pipe 15 and have 0 (zero) payload length. Consequently, the Length word in the packet header is 1. The options for the generation of an ACK are:

No ACK generation, unless the Force ACK bit is set in the header.

Logical Pipe Assignment (to TFB)

The serial interface supports 16 logical pipes which are used to separate packets into different logical data streams on the same physical channel. Assignment of these is detailed in the following tables:

Upstream Logical Pipe ID assignments
Pipe ID	Pipe Name	Description
0	Monitor Configuration	Monitor Configuration data upload pipe
1	Configuration	Forwards the packets to the configuration bus master in the FPGA. These payloads must have the correct structure.
2	Bootloader	Forwards the packets to the input buffer
3 to 15	Reserved	Currently unallocated.

Downstream Logical Pipe ID assignments
Pipe ID	Pipe Name	Description
0	Reserved
1	Configuration	Return packet from the configuration interface will have this pipe id.
2	ADC Data	Packets containing data from all ADC channels will have this pipe ID
3	Reserved
4	Trip-T Timestamps	Timestamp data from all Trip-Ts
5	Reserved
6	Reserved
7	Reserved
8	Reserved
9	Reserved
10	Reserved
11	Reserved
12	Monitor Data	Status and Data Packets from the Monitor Player
13	Reserved
14	Reserved
15	ACK/NACK	Acknowledge/No Acknowledge Packets will have this

Resetting the TFB

The TFB will be reset if a high level persists on the Trigger line for more than 100 clock cycles (1 microsecond). Once a reset has been initiated in the fashion, the TFB will remain in reset and be unresponsive to any communication for approximately 50ms after the Trigger line has been taken low again. This time is required to allow the device to re-lock to the input clock. The clock must be stable during the reset time.