Trip-T Front End Board Documentation Home
Triggers
Note: This page refers to the User Firmware, a description of TFB
triggers for the Bootloader firmware can be found
here
There are two ways of triggering the TFB:
- through the configuration bus, by writing to register 0;
- through the dedicated trigger input using the trigger structure
1) CONFIGURATION BUS
The configuration bus trigger vector mappings for method 1 when the
user firmware is booted are as follows.
- 0x1 = spill start
- 0x2 = trigger ADC packet send in managed mode.
- 0x4 = trigger time stamp packet send in managed mode.
- 0x8 = Start I2c Transaction
- 0x10 = Trigger Prom Read ID Code
- 0x20 = Trigger Prom Read User Code
- 0x40 = Trigger TripT configuration interface transaction.
- 0x80 = Trigger load HV trim DAC load.
- 0x100 = Trigger PROM TAP Reset
- 0x200 = Trigger Monitor Player Command Buffer Readback
- 0x400 = Load Spill Number Offset
- 0x800 = Issue I2C Timeout Reset
2) DEDICATED TRIGGER INPUT
The trigger line has 12 independent triggers accessible through the
dedicated trigger input signal pair. The following triggers are
allocated, the rest are reserved.
- 0x1 = spill start with coarse time stamp counter reset.
- 0x2 = spill start without coarse time stamp counter reset.
- 0x4 = ADC packet readout trigger
- 0x8 = Time stamp packet readout trigger
- 0x10 = unallocated
- 0x20 = unallocated
- 0x40 = unallocated
- 0x80 = Reset Coarse Time Stamp Counter
- 0x100 = Cosmic Accept
- 0x200 = unallocated
- 0x400 = unallocated
- 0x800 = Cosmic Halt
DEDICATED TRIGGER INPUT FORMAT and TIMING
The trigger input is a 16 bit word, but each bit is triplicated. The 16-bit word is
1001(0xNNN) where 0xNNN is the value from the above table.
So for spill start with coarse time stamp counter reset, the trigger word would be
1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 , but it would actually be sent as
111 000 000 111 000 000 000 000 000 000 000 000 000 000 000 111 .
In spill mode there is a fixed timing between the leading edge of the first bit in the
header and the beginning of the first integration cycle, given by
740 nsec + (trigger delay value) + (reset time value)
where (trigger delay value) is the value in the Trigger Delay Register (x 10 nsec)
(address 6 in register map)
and (reset time value) is the value of the Preamp Reset Duration (x 10 nsec)
(address 519 in register map)
(Note that the actual Preamp reset duration is 10 nsec longer than the value loaded
into register 519)
e.g. for trigger delay value = 0, and reset time value = 9, the time between the
leading edge of the first bit in the trigger word header and the beginning of the
first integration cycle will be 830 nsec.