| Address | Name | Description | |
| 0 | Trigger/Firmware Load Register |
11:0=trigger vector. A 1 present activates that trigger line. 15:12=trigger duration. The number here represents the number of 50ns clock counts the trigger is asserted for. This register does not retain the data written to it. Reading from register 0 provides the following diagnostic information: 15:8 not used bit 7: fsm busy bit 6: LM92 signal (not useful) bit 5: LM92 signal (not useful) bit 4: internal cosmic accept bit 3: readout active bit 2: timestamp buffer empty if set bit 1: ADC data buffer empty if set bit 0: 1=in bootloader revision, 0=in user revision |
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| 1 | Revision Register | Controls the firmware revisioning circuit. Writing a 0 reloads the TFB firmware into the Bootloader, writing a 1 reloads the firmware in User Mode. | |
| 2 | HV enable | 0 = set enables the HV, cleared disables it. 1 = set enables Link Calibration Mode, cleared is normal readout mode. 15:2 = reserved. |
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| 3 | Trigger Counter Offset(15:0) | Least significant 16 bits of the trigger counter. The full 32 bit number is the start point for the trigger counter. | |
| 4 | Trigger Counter Offset(31:16) | Most significant 16 bits of the trigger counter. The full 32 bit number is the start point for the trigger counter. | |
| 5 | Spill Mode Register | Bits 7:0 Reserved Bit 8: Spill Mode: 0=normal, 1=Cosmic Bit 9: 0= normal cosmic mode, 1=Local Cosmic Loopback (a cosmic primitive will cause local readout.) Bits 15:10 Reserved. |
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| 6 | Trigger Delay Register | 4:0 = amount to delay the application of the trigger by. LSB = 10ns 15:5 = reserved. |
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| 10 | Clock Phase Control | 15:8 = Upstream sample point; 7:0=return phase. Range=0-255 inclusive. 0x80=zero phase shift, step size ~ 40ps. |
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| 64 | HV Trim DAC Data Register |
15:12 = Control bits. 11:0=Data bits; 8 bits aligned to bits 11:4; (3:0 reserved, should be set to 0). |
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| 65 | HV Trim DAC Mux Register | 2:0 set the DAC selected for loading. 15:3 are unused. | |
| 80 | Minor Firmware Revision | Contains the Minor Firmware Build Revision Number | |
| 81 | Major Firmware Build Revision | Contains the Major Firmware Build Revision Number | |
| 82 | Build UTC(15:0) | Least significant 2 bytes of the 32 bit UTC from the firmware build time. | |
| 83 | Build UTC(31:16) | Most significant 2 bytes of the 32 bit UTC from the firmware build time. | 96 | I2C Data Input Register | Data placed here will be transferred to the I2C slave being addressed during a write transaction. | 97 | I2C Slave Address and Control Register | 6:0 Slave address, 7: 1=write, 0=read 8: 1=16 bit transfer, 0=8 bit transfer 9: 1=transfer slave internal address byte first, 0=don't. 15:10 reserved |
98 | I2C Slave Internal Address Register |
7:0 Slave address, 15:8 reserved. |
100 | I2C Read Data Register | Results from a read operation can be read from here. A byte transfer will return the data in bits 15:8. | 101 | I2C Status Register |
0: Read transaction data ready 1: Transfer in progress 7:2 Internal debugging signals 8: Set=Monitor Active, Cleared=Monitor Inactive (this will appear in rev 0.65 and above.) 15:9 Set to zero. |
102 | I2C Monitor Interval Register | Determines the length of the monitor sleep | 103 | I2C Monitor Control Register | Bit 0: Set, this bit activates the monitor, cleared it deactivated it. 1: Set, This bit resets the internal address management for the monitor command buffer. NB this bit must be cleared before a new command set may be uploaded. |
120 | Prom User Code(15:0) | TFBId is the only thing in here | 121 | Prom User Code(31:16) | same for all PROMs | 122 | Prom ID Code(15:0) | 123 | Prom ID Code(31:0) |
| 512 | Discriminator Enable Mask A | 15:0 bits are anded with Trip-T discriminator inputs. Default=0x0000. | 513 | Discriminator Enable Mask B | 15:0 bits are anded with Trip-T discriminator inputs. Default=0x0000. | 514 | Discriminator Enable Mask C | 15:0 bits are anded with Trip-T discriminator inputs. Default=0x0000. | 515 | Discriminator Enable Mask D | 15:0 bits are anded with Trip-T discriminator inputs. Default=0x0000. |
| 516 | Global enable | 15:4 =
reserved; 3:0 = Global Enables for Trip-Ts D,C,B,A
respectively. Resets to 0x0, setting a 1 enables the corresponding Trip-T. | |
| 517 | Coarse timestamp enable | Bit 0 should be set to enable the coarse timestamp counter (this register used to be number of integration cycles till this was fixed at 23) |
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| 518 | Integration Duration | 15:0=unsigned length of integration period in 10ns steps. min=4. A value of 54 will correspond to an integration period of 540 nsec. | |
| 519 | Pre-amp Reset Duration | 15:0 unsigned length of pre-amp reset period in 10ns steps. min=4. Note: The actual reset duration is one 100 MHz clock cycle greater than the value set, so a value of 9 will correspond to a reset period of 100 nsec. | |
| 520 | TripT Programming Interface Data Reg. | 9:0=data. 14:10=reserved. 15=10 bit transaction. When set, the interface will perform a 10bit transaction, otherwise it will be 8 bits (refer to the TripT manual for details of this interface). 14:10=reserved. |
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| 521 | TripT Programming interface Command Reg. | 4:0 = TripT internal Address. 6:5 = TripT Mux control bits: 00=A, 01=B, 10=C, 11=D. 9:7 = TripT Command designator (TripT Manual.). 10 = Mux Mode: 1=command, 0=operation. This bit must be set for the programming interface to work, and must be cleared before the TripT Control FSM will sequence the chip correctly. |
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| 600 | Trip T Programming Interface ReadBack Register. | Data readback from the programming interface can be read from here when the transaction is complete. Readback is currently untested, although the write has been shown to work. | |
| 522 | Readout Control Register | 0: When set this makes the ADC data formatter wait for the readout trigger. 1:5 = reserved. 6: when set, this makes the time stamp packet formatter for all TripT's wait for a readout trigger. |
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| 523 | Test Trigger Start Offset | 13:0=test trigger offset count. Nx10ns, defines the start point of the test trigger 14=Test trigger output select: 0=Pipeline reset, 1=test trigger 15=no longer used (was Test trigger output enable). See register 535 for the Test Trigger End Offset. |
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| 524 | Calibration Pulse Mask Register | 15:0 = active high mask for the test pulse circuit trigger outputs (See TFB schematics). | |
| 525 | Calibration Trigger Offset | 15:0=unsigned calibration pulse offset, Nx10ns. | |
| 526 | Cosmic Primitive Length Register | Controls the duration for which the primitive accept is asserted. 8bit, 10ns per LSB. | |
| 527 | Trip-T A cosmic enable mask | one bit per channel: "1" permits the channel top participate in the cosmic primitive generation. | |
| 528 | Cosmic Accept Threshold | 7 bit number. The cosmic accept is asserted if the number of simultaneously active discriminators exceeds this value. | |
| 529 | Trip-T B cosmic enable mask | one bit per channel: "1" permits the channel top participate in the cosmic primitive generation. | |
| 530 | Cosmic Window | 4 bit number. The accept gate length: 10ns LSB. | |
| 531 | Trip-T C cosmic enable mask | one bit per channel: "1" permits the channel top participate in the cosmic primitive generation. | |
| 532 | Cosmic Mode Register |
Bit 0: 0=off-axis mode, 1=INGRID mode. Bit 1: 0=individual channel operation, 1=paired channel operation. Bit 2: 0=opposite paired operation, 1=adjacent paired operation. Bit 3: 0=standard primitive polarity, 1=inverted primitive polarity. Bit 4: 0=Test Trigger, 1=Cosmic trigger (ensure this is set to 1 if you want cosmic triggers). Bit 5: in INGRID mode 0 (default) means (A OR B) OR (C OR D) 1 means (A OR B) AND (C OR D) |
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| 533 | Trip-T D cosmic enable mask | one bit per channel: "1" permits the channel to participate in the cosmic primitive generation. | |
| 535 | Test Trigger End Offset | 15:0 defines the end point of the test trigger Nx10ns. Note: this number must be larger than Test Trigger Start Offset for a pulse to be emitted. |
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