| Address | Name | Description | |
| 0 | Trigger/Firmware Load Register |
11:0=trigger vector. A 1 present activates that trigger line. 15:12=trigger duration. The number here represents the number of 50ns clock counts the trigger is asserted for. This register does not retain the data written to it. Reading from register 0 determines whether the TFB is booted in the user firmware or the booloader. The LSB=1 for bootloader, and 0 for user mode. |
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| 1 | Revision Register | Controls the firmware revisioning circuit. Writing a 0 reloads the TFB firmware into the Bootloader, writing a 1 reloads the firmware in User Mode. | |
| 2 | HV enable | 0 = reserved (there is no facility to switch on the HV in the Bootloader) 1 = set enables Link Calibration Mode, cleared is normal readout mode. 15:2 = reserved. |
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| 10 | Clock Phase Control | 15:8 = Upstream sample point; 7:0=return phase. Range=0-255 inclusive. 0x80=zero phase shift, step size ~ 40ps. |
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| 64 | HV Trim DAC Data Register |
15:12 = Control bits. 11:0=Data bits; 8 bits aligned to bits 11:4; (3:0 reserved, should be set to 0). |
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| 65 | HV Trim DAC Mux Register | 2:0: Mux Address for the TrimDACs. These are arranged so that 0=TripT A, Lower Channels, 1=TripT A Upper channels ... 7=TripT D Upper channels 15:3: Reserved |
71 | JTAG Controller Status Register |
3:0: hold a non zero number when an error has occurred. 4: JTAG controller busy when set 5: JTAG controller stalled when set (awaiting data) 6: PROM Erasure in progress 7: Firmware Upload FIFO Empty when set 8: Firmware Upload FIFO Full when set 9: Firmware Load Complete 10: Readback in progress 11: Firmware Upload FIFO 75% Full when set 12: Firmware Upload FIFO 75% Empty when set 13: Overflow occurred. This is a critical error. 15:14: 00. |
72 | JTAG Controller Error Register | When an error is encountered, this register holds the contents of the PROM status register. | 96 | I2C Data Input Register | Data placed here will be transferred to the I2C slave being addressed during a write transaction. | 97 | I2C Internal Slave Address Register | 7:0 Slave internal address register, 15:8 reserved |
98 | I2C Slave Address Register |
6:0 Slave address, 15:7 reserved. |
100 | I2C Status Register |
0: Read transaction data ready 1: Transfer in progress 7:2 Internal debugging signals 8: Set=Monitor Active, Cleared=Monitor Inactive (this will appear in rev 0.65 and above.) 15:9 Set to zero. |
101 | I2C | 102 | I2C Monitor Interval Register | Determines the length of the monitor sleep | 103 | I2C Monitor Control Register | Bit 0: Set, this bit activates the monitor, cleared it deactivated it. 1: Set, This bit resets the internal address management for the monitor command buffer. |