Provisional Programme Timetable

Start Time

22nd September
Monday

23rd September
Tuesday

24th September
Wednesday

25th September
Thursday

26th September
Friday

9.00


Radiation Hard Electronics (LT1)

Quality Management Systems (LT1)

Maintenance and Reliability (LT1)

Panel A Discussion (LT1)

9.45

Registration (F)

Testing Electronics Systems (LT1)

Packaging and Interconnection(LT1)

Optical Link Technology (LT1)

10.30

Coffee (F)

Coffee (F)

Coffee (F)

Coffee (F)

Coffee (F)

11.00

Registration (F)

LT1: Optical link, Front end electronics, Rad. hard
LT2:
DAQ, Trigger & Muon Systems

LT2: Optical link, Front end electronics, Rad. hard
LT1:
DAQ, Trigger & Muon Systems

LT1: Optical link, Front end electronics, Rad. hard
LT2:
DAQ, Trigger & Muon Systems

Panel B Discussion (LT1)

12.30

Lunch

(MDH)

Lunch

(MDH)

Lunch

(MDH)

Lunch

(MDH)

Lunch

(MDH)

14.00

ATLAS System Summary (LT1)

LT1: Optical link, Front end electronics, Rad. hard
LT2:
DAQ, Trigger & Muon Systems

LT2: Optical link, Front end electronics, Rad. hard
LT1:
DAQ, Trigger & Muon Systems

LT1: Optical link, Front end electronics, Rad. hard
LT2:
DAQ, Trigger & Muon Systems

 

End of Workshop

14.45

CMS System Summary (LT1)

15.30

Coffee (F)

Coffee (F)

Coffee (F)

Coffee (F)

16.00

Alice System Summary (LT1)

LT1: Optical link, Front end electronics, Rad. hard
LT2:
DAQ, Trigger & Muon Systems

LT2: Optical link, Front end electronics, Rad. hard
LT1:
DAQ, Trigger & Muon Systems

ROSE Presentation (LT1)

16.45

LHC-B System Summary (LT1)

Break

17.30

Break

Break

Break

18.30

LEB

Reception

(CR)



19.30




LEB

Dinner

Science

Museum

20.30




21.30




Key:

LT1

Lecture Theatre 1. Level 3 Blackett Laboratory.

LT2

Lecture Theatre 2. Level 1 Blackett Laboratory.

LT3

Lecture Theatre 3. Level 1 Blackett Laboratory.

F

Level 2 Foyer. Blackett Laboratory.

CR

Level 8 common room, Blackett Laboratory.

MDH

Main Dining Hall. Ground Level, Sherfield building.


Detailed Timetable

The number of talks scheduled in Session A is currently over 35. The speaking time allocated to each talk will typically be 15 minutes. Speakers are requested to keep their contribution within this limit so that reasonable time for discussion is available. The chairman will decide whether this will follow each talk or be at the end of each partial session.

Monday 22 September 1997

10.00

12.30

Registration

 

Level 2 foyer

12.30

14.00

Lunch

Main Dining Hall, Sherfield Building, Ground Level

 

14.00

17.45

Session 1

Main Lecture Hall, Level 3

Chairman -

 

P. Sharp

14.00

14.15

Welcome & Opening Remarks

P Sharp / P Dornan

14.15

15.00

Atlas System Summary

P Farthouat

15.00

15.45

CMS System Summary

 

G Hall

15.45

16.15

Coffee

 

Level 2 foyer

16.15

17.00

Alice System Summary

F Formenti

17.00

17.45

LHC-B System Summary

 

J Christiansen

17.45

18.30

Break

 

18.30

20.30

Workshop Reception
Sponsored by CAEN, Wiener and Southern Scientific

Level 8 Common Room

Tuesday 23 September 1997

9.00

10.30

Session 2

Main Lecture Hall, Level 3

Chairman -

 

M. Turala

9.00

9.45

Radiation-Hardened Microelectronics

P. Winokur (Sandia)

9.45

10.30

Design-For-Test and its evolution into Built-In Self Test

 

B.Bennetts (LogicVision)

 

10.30

11.00

Coffee

Level 2 foyer

 

11.00

12.30

Session 3

 

Lecture Halls 1 & 2

Working Group A
Front-end Electronics, Radiation Hard & Optical Links

Lecture Hall 1
G Stefanini

 

11.00

11.20

Applying Commercial Best Practices to Hardened Device Production

J Swonger

11.20

11.40

Further Radiation Hardened SOI CMOS Technology

M Liu

11.40

12.00

Recent Characterisation of DMILL Rad-Hard Mixed Analogue-Digital Technology for High Energy Physics Applications

M Dentan

12.00
12.15

12.15
12.30

Total dose behaviour of submicron and deep submicron CMOS technologies

(i) P Jarron
(ii) A Marchioro

12.30

12.45

Total dose behaviour of commercial submicron VLSI technologies at low dose rate

 

A Giraldo

Working Group B
Data Acquisition and Trigger and Muon Systems

Lecture Hall 2
W Smith, N Ellis

 

11.00

11.30

The First Level Muon Trigger of ATLAS in the Barrel Region

E Petrolo

11.30

11.50

Front-end Electronics of the ATLAS Precision Muon Drift Chambers

W Riegler

11.50

12.10

TDC Architecture Study for the ATLAS Muon Tracker

Y Arai

12.10

12.30

High Speed Data Transmission and Compression for the CMS RPC Muon Trigger

 

K Pozniak

 

12.30

14.00

Lunch

Main Dining Hall, Sherfield Building, Ground Level

 

14.00

17.30

Session 4

 

Lecture Halls 1 & 2

Working Group A
Front-end Electronics, Radiation Hard & Optical Links

Lecture Hall 1
G Stefanini

 

14.00

14.15

Radiation hardening of submicron CMOS using commercial radhard technology

R Sharman

14.15

14.35

A Single Chip Implementation of the Binary Readout Architecture for Silicon Strip Detectors in the ATLAS Silicon Tracker

F Anghinolfi

14.35

14.55

The APV6 Readout Chip for CMS Microstrip Detectors

M Raymond

14.55

15.15

APVD: a CMOS mixed analog-digital Circuit for the Silicon Tracker in CMS

R Turchetta

15.15

15.35

Radiation Tolerance Studies of the APV6 Chip

 

J Matheson

Working Group B
Data Acquisition and Trigger and Muon Systems

Lecture Hall 2
W Smith, N Ellis

 

14.00

14.20

A 16-Channel, 96-Cell Switched Capacitor Array for the CMS Endcap Muon System

R Breedon

14.20

14.40

The Track Finder of the CMS 1st level Muon Trigger

T Wildschek

14.40

15.00

32 channel TDC with on-chip buffering and trigger matching

J Christiansen

15.00

15.20

A High Resolution Time to Digital Converter Based on an Array of Delay Locked Loops

M Mota

15.20

15.30

Discussion

 

 

 

15.30

16.00

Coffee

Level 2 foyer

 

Working Group A
Front-end Electronics, Radiation Hard & Optical Links

Lecture Hall 1
G Stefanini

 

16.00

16.20

ALICE128C: A CMOS Full Custom ASIC for the Readout of Silicon Strip Detectors in the ALICE Experiment

L Herbrard

16.20

16.40

HELIX128S-2 - A Readout Chip for the HERA-B Silicon Vertex and Inner Tracking Detectors

W Fallot-Burghardt

16.40

17.00

A 128 Channel Readout Chip with Real Time Data Sparsification and Multi-hit Capability

P Fischer

17.00

17.20

Overview of the front-end electronics in the Atlas LAr calorimeter

C de la Taille

17.20

17.40

Controlling the Switched Capacitor Array Based Frontend Readout at ATLAS

J Pinfold

17.40

18.00

Discussion

 

Working Group B
Data Acquisition and Trigger and Muon Systems

Lecture Hall 2
W Smith, N Ellis

 

16.00

16.20

A Hybrid Approach for the ATLAS Level-2 Trigger

M Sessler

16.20

16.40

A Lifetime Based Second Level Beauty Trigger using Pixels in ATLAS

P Morrettini

16.40

17.00

Development of the ALICE Detector Data Link Prototype

G Rubin

17.00

17.20

New Developments in ALICE trigger electronics

O Villalobos Baillie

 

Wednesday 24 September 1997

9.00

10.30

Session 5

Main Lecture Hall, Level 3

Chairman -

 

U. Straumann

9.00

9.45

Turning plans into reality

D. Gee (Hewlett Packard)

9.45

10.30

Flip Chip Interconnection: Dream or Nightmare?

G. Riley (HyComp)

 

10.30

11.00

Coffee

Level 2 foyer

 

11.00

12.30

Session 6

 

Lecture Halls 1 & 2

Working Group A
Front-end Electronics, Radiation Hard & Optical Links

Lecture Hall 2
G Stefanini

 

11.00

11.20

The ATLAS Pixel Detector System Architecture

G Darbo

11.20

11.40

Performance of ATLAS pixel prototype chips

P-V Bonzom

11.40

12.00

Results from a Sparsified Pixel Readout for the CMS Pixel Detector

G Grim

12.00

12.20

From a 50um readout element to a 50 million cell detector: aspects of the design of a pixel system.

M Campbell

12.20

12.30

Discussion

 

Working Group B
Data Acquisition and Trigger and Muon Systems

Lecture Hall 1
W Smith, N Ellis

 

11.00

11.20

Implementation of the Calibration Signals for the ATLAS Liquid Argon Calorimeter using the TTC System

J Renardy

11.20

11.40

Analogue Summation for the Scintillating Tile Calorimeter

J Seixas

11.40

12.05

A Prototype 160 Mbit/s Backplane for the ATLAS Level-1 Calorimeter Trigger

E Eisenhandler

12.05

12.30

Performance of the Front-End Demonstrator System for the ATLAS Level-1 Calorimeter Trigger

 

U Pfeiffer

 

12.30

14.00

Lunch

Main Dining Hall, Sherfield Building, Ground Level

 

14.00

17.30

Session 7

 

Lecture Halls 1 & 2

Working Group A
Front-end Electronics, Radiation Hard & Optical Links

Lecture Hall 2
G Stefanini

 

14.00

14.20

A system for timing distribution and control of front end electronics for the CMS tracker

A Marchioro

14.20

14.40

A PLL-Delay ASIC for Clock Recovery and Trigger Distribution in the CMS Tracker

P Placidi

14.40

15.00

Electronic Calibration of the Electromagnetic Calorimeter of CMS

G Bohner

15.00

15.20

Testing Front-end Electronics for High Energy Physics Detectors

D De Venuto

15.20

15.30

Discussion

 

Working Group B
Data Acquisition and Trigger and Muon Systems

Lecture Hall 1
W Smith, N Ellis

 

14.00

14.20

A Digital Readout System for High Resolution Calorimetry

M Hansen

14.20

14.40

The CMS Calorimeter Trigger

G Heath

14.40

15.00

Digital Data Processing for CMS Calorimeter LVL1 Trigger

P Busson

15.00

15.20

Trigger Synchronization Circuits in CMS

J Varela

15.20

15.40

High-speed Data Processing for CMS Calorimeter Trigger

 

W Smith

 

15.30

16.00

Coffee

Level 2 foyer

 

Working Group A
Front-end Electronics, Radiation Hard & Optical Links

Lecture Hall 2
G Stefanini

 

16.00

16.20

The DIRC front-end electronics chain for BABAR

D Breton

16.20

16.40

A Discriminator Chip for Time of Flight Measurements in Alice

C Neyer

16.40

17.00

ADELINE: Analog Memories for Nuclear Data Sampling

S Panebianco

17.00

17.20

Front-End Electronics for a TPC-Detector

R Baur

17.20

17.40

CMOS Ultra Low Noise Front-End for X-Ray Spectroscopy

C Marzocca

17.40

18.00

A Semicustom Array for Creating High-Speed Front-End LSICs

 

A Goldsher

Working Group B
Data Acquisition and Trigger and Muon Systems

Lecture Hall 1
W Smith, N Ellis

 

16.00

16.20

A Demonstrator for the ATLAS Level-1 Central Trigger Processor

I Brawn

16.20

16.40

The Read-Out crate for the ATLAS DAQ/EF prototype

D Francis

16.40

17.20

A Common Control System for the LHC Experiments

D Myers

 

Thursday 25 September 1997

9.00

10.30

Session 8

Main Lecture Hall, Level 3

Chairman -

 

M. Letheren

9.00

9.45

Maintenance and Reliability

P. Smith (Matra-Marconi)

9.45

10.30

Optical Link Technology: Silicon Optical Bench Technology

G. Chiaretti (Italtel)

 

10.30

11.00

Coffee

Level 2 foyer

 

11.00

12.30

Session 9

 

Lecture Halls 1 & 2

Working Group A
Front-end Electronics, Radiation Hard & Optical Links

Lecture Hall 1
G Stefanini

 

11.00

11.20

Optical Links for the ATLAS Semiconductor Tracker

A Weidberg

11.20

11.40

Final Results of Radiation Hardness and Life Time Studies of LEDs and VCSELs for Optical Links of the ATLAS Inner Detector

K Borer

11.40

12.00

Development of Rad-hard Laser-based Optical Links for CMS Front-ends

F Vasey

12.00

12.20

Radiation Damage Studies of Opto-electronic Components for the CMS Tracker Optical Links

K Gill

12.20

12.30

Discussion

 

Working Group B
Data Acquisition and Trigger and Muon Systems

Lecture Hall 2
W Smith, N Ellis

 

11.00

11.30

The CMS Tracker Front-End Driver Prototype

R Halsall

11.30

12.00

ATM Based Event Building at CDF

S Sumorok

12.00

12.30

CMS Dual Port Memory Structures

 

A Fucci

 

12.30

14.00

Lunch

Main Dining Hall, Sherfield Building, Ground Level

 

14.00

15.30

Session 10

 

Lecture Halls 1 & 2

Working Group A
Front-end Electronics, Radiation Hard & Optical Links

Lecture Hall 1
G Stefanini

 

14.00

14.20

An integrated Laser Driver Array for Analogue Data Transmission in the LHC Experiments

P Moreira

14.20

14.40

Characterization of optical data links for the CMS experiment

V Arbet-Engels

14.40

15.00

Simulation and Characterisation of the CMS Tracker Optical Readout Chain

G Cervelli

15.00

15.20

Analogue Optical Links for the Frond-end Read-out of the ATLAS Liquid Argon Calorimeter

O Martin

15.20

15.30

Discussion

 

Working Group B
Data Acquisition and Trigger and Muon Systems

Lecture Hall 2
W Smith, N Ellis

 

14.00

14.20

CMS Front-end Model and VME64 Sequencer

A Racz

14.20

14.40

CMS FPGA Dual Port Memory Prototypes

D Gigi

14.40

15.00

CMS Dual PCI Input-Output Processor

J Ero

15.00

15.30

CMS Data Links and Event Builder Studies

 

T Ladzinski

 

15.30

16.00

Coffee

Level 2 foyer

 

16.00

16.30

ROSE: R & D on silicon for future experiments

 

S. Watts

16.30
16.30

18.30
17.30

Break
LEB members only: LEB meeting

 

19.00

23.00

Workshop Dinner
Doors open at 19.00, reception starts at 19.15

Flight Gallery
Science Museum

 

Friday 26 September 1997

9.00

12.30

Session 11
Chairman-

 

Main Lecture Hall, Level 3
G. Hall

9.00

10.30

Panel Discussion
Working Group A

 

V. Radeka

 

10.30

11.00

Coffee

Level 2 foyer

 

11.00

12.30

Panel Discussion
Working Group B

 

S. Cittolin

12.30

12.45

Closing Remarks

 

12.30

14.00

Lunch

Main Dining Hall, Sherfield Building, Ground Level

 

14.00

End of Workshop


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Last updated 11/9/97

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