On 18th March 2013, Avago proudly announced the release of MiniPODs capable of operating at 14Gbps. This will, in theory, extend the bandwidth of the MP7 from the already impressive 0.75+0.75Tbps, up to a phenomenal 0.94+0.94Tbps.

We eagerly await the results of testing the MP7 with these new optics!

See here for the Avago press release

Master Procesor, Virtex-7
The Imperial Master Processor, Virtex-7.

The Imperial Master Processor, Virtex-7 (MP7) is a high-performance all-optical, data-stream processor designed to operate in the challenging conditions of the CMS trigger system at the Large Hadron Collider (LHC). Utilising the high performance Xilinx Virtex-7 FPGA and state-of-the-art fibre optics technologies, the MP7 has the capability to input and output data at a rate of 3/4 Tbit per second, equivalent to the mean global traffic of the entire Internet in 2001. These features are crucial in the operation of the trigger at the LHC where a latency budget of 3.2μs is afforded to readout and process the large volume of data from the detector subsystems, equivalent to processing data at a rate of up to 10 Tbits per second. The MP7 is the baseline trigger processor board for the CMS calorimeter trigger upgrade, whose capabilities are expected to achieve an improvement in the physics performance of the CMS detector under the more challenging full-energy and high-luminosity conditions that will be experienced in the upgraded LHC beam.

  • A powerful processing capability provided by a high-performance Xilinx Virtex-7 FPGA.
  • A large total optical bandwidth input and output of up to 740 Gbps in each direction.
  • LVDS I/O with speeds of up to 50 Gbps.
  • 288 Mbit fast QDR II+ SRAM, giving memory access of up to 550MHz DDR (1100MHz) per chip.
  • Reconfigurable data-stream processing, allowing the board to be adapted to changes in requirements.
  • On-board monitoring provides real-time information of temperature, voltages, current drawn and humidity.

The design of the MP7 features flexible I/O with a single optical form-factor for the sending and receiving of data which offers several distinct advantages. With this design, the board ceases to have a specific role and becomes a truly generic stream-processing engine. The application of the board to a specific task is therefore no longer restricted by the bandwidth and compatibility of each type of interface, but only by the total bandwidth. The specialisation required for a task is therefore fully contained within the programming of the board and the interconnections between boards, greatly simplifying modifications to the operation of the board. The reliability of the MP7's high speed links have been well tested, with in excess of an exabit of data being transferred so far without error.

Eye diagram - Optical scope Eye diagram - Optical scope
Eye diagrams measured from the MP7. (Left) Optical measurement on an oscilloscope (Right) Measurement from the on-chip Xilinx IBERT.

The processing power and I/O capabilities of the MP7 are cutting-edge. As seen below, the optical I/O of a single MP7-485 processor board exceeds the mean data rate of the entire Internet in late 2000 and a single MP7-690 processor board could have handled the entire Internet in early 2001. These capabilities mean the number of boards required to perform the trigger system operation in the upgraded LHC conditions is significantly reduced, with a trigger system built entirely of MP7's requiring 1/40 of the rack space occupied by that of the current system.

The MP7 I/O capabilities
A comparison of the MP7 I/O capabilities with the mean instantaneous traffic of the Internet as reported by Cisco systems.

The high performance and I/O bandwidth of the MP7 make it a prime candidate for the proposed future CMS tracker trigger upgrade. Requiring the processing of a large number of hardware channels, the tracker trigger presents an extremely challenging task however would be well suited to the abilities of the MP7.